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IEEE; 2013:83-88. doi:<a href=\"https://doi.org/10.1109/DFT.2013.6653587\">10.1109/DFT.2013.6653587</a>","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2013, title={A fast TCAD-based methodology for Variation analysis of emerging nano-devices}, DOI={<a href=\"https://doi.org/10.1109/DFT.2013.6653587\">10.1109/DFT.2013.6653587</a>}, booktitle={2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}, year={2013}, pages={83–88} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “A Fast TCAD-Based Methodology for Variation Analysis of Emerging Nano-Devices.” <i>2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)</i>, IEEE, 2013, pp. 83–88, doi:<a href=\"https://doi.org/10.1109/DFT.2013.6653587\">10.1109/DFT.2013.6653587</a>.","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013, pp. 83–88.","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani, and Giovanni De Micheli. “A Fast TCAD-Based Methodology for Variation Analysis of Emerging Nano-Devices.” In <i>2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)</i>, 83–88. IEEE, 2013. <a href=\"https://doi.org/10.1109/DFT.2013.6653587\">https://doi.org/10.1109/DFT.2013.6653587</a>.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., &#38; De Micheli, G. (2013). A fast TCAD-based methodology for Variation analysis of emerging nano-devices. In <i>2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)</i> (pp. 83–88). IEEE. <a href=\"https://doi.org/10.1109/DFT.2013.6653587\">https://doi.org/10.1109/DFT.2013.6653587</a>","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli, “A fast TCAD-based methodology for Variation analysis of emerging nano-devices,” in <i>2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)</i>, 2013, pp. 83–88."},"extern":"1","date_created":"2019-07-10T12:10:17Z","type":"conference","department":[{"_id":"78"}]},{"publication":"2013 14th Latin American Test Workshop-LATW","citation":{"ieee":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study,” in <i>2013 14th Latin American Test Workshop-LATW</i>, 2013, pp. 1–6.","apa":"Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., &#38; De Micheli, G. (2013). Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In <i>2013 14th Latin American Test Workshop-LATW</i> (pp. 1–6). IEEE. <a href=\"https://doi.org/10.1109/LATW.2013.6562673\">https://doi.org/10.1109/LATW.2013.6562673</a>","chicago":"Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” In <i>2013 14th Latin American Test Workshop-LATW</i>, 1–6. IEEE, 2013. <a href=\"https://doi.org/10.1109/LATW.2013.6562673\">https://doi.org/10.1109/LATW.2013.6562673</a>.","short":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6.","mla":"Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” <i>2013 14th Latin American Test Workshop-LATW</i>, IEEE, 2013, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/LATW.2013.6562673\">10.1109/LATW.2013.6562673</a>.","bibtex":"@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}, DOI={<a href=\"https://doi.org/10.1109/LATW.2013.6562673\">10.1109/LATW.2013.6562673</a>}, booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013}, pages={1–6} }","ama":"Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: <i>2013 14th Latin American Test Workshop-LATW</i>. IEEE; 2013:1-6. doi:<a href=\"https://doi.org/10.1109/LATW.2013.6562673\">10.1109/LATW.2013.6562673</a>"},"extern":"1","date_created":"2019-07-10T12:10:18Z","type":"conference","department":[{"_id":"78"}],"year":"2013","status":"public","title":"Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study","author":[{"last_name":"Gaillardon","first_name":"Pierre-Emmanuel","full_name":"Gaillardon, Pierre-Emmanuel"},{"last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","id":"61186"},{"full_name":"De Micheli, Giovanni","first_name":"Giovanni","last_name":"De Micheli"}],"date_updated":"2022-01-06T06:50:50Z","page":"1-6","language":[{"iso":"eng"}],"_id":"10775","publisher":"IEEE","user_id":"3118","doi":"10.1109/LATW.2013.6562673"},{"user_id":"398","_id":"13645","publisher":"Springer","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:40Z","year":"2013","title":"On Semeai Detection in Monte-Carlo Go.","status":"public","author":[{"first_name":"Tobias","last_name":"Graf","full_name":"Graf, Tobias"},{"full_name":"Schäfers, Lars","first_name":"Lars","last_name":"Schäfers"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T22:50:51Z","publication":"Proceedings of the International Conference on Computers and Games (CG)","citation":{"bibtex":"@inproceedings{Graf_Schäfers_Platzner_2013, title={On Semeai Detection in Monte-Carlo Go.}, booktitle={Proceedings of the International Conference on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schäfers, Lars and Platzner, Marco}, year={2013} }","ama":"Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: <i>Proceedings of the International Conference on Computers and Games (CG)</i>. Springer; 2013.","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” <i>Proceedings of the International Conference on Computers and Games (CG)</i>, Springer, 2013.","chicago":"Graf, Tobias, Lars Schäfers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In <i>Proceedings of the International Conference on Computers and Games (CG)</i>. Springer, 2013.","short":"T. Graf, L. Schäfers, M. Platzner, in: Proceedings of the International Conference on Computers and Games (CG), Springer, 2013.","ieee":"T. Graf, L. Schäfers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go.,” in <i>Proceedings of the International Conference on Computers and Games (CG)</i>, 2013.","apa":"Graf, T., Schäfers, L., &#38; Platzner, M. (2013). On Semeai Detection in Monte-Carlo Go. In <i>Proceedings of the International Conference on Computers and Games (CG)</i>. Springer."}},{"date_created":"2017-10-17T12:42:35Z","file":[{"creator":"florida","date_created":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf","file_size":822680,"access_level":"closed","relation":"main_file","date_updated":"2018-03-15T10:36:08Z","file_id":"1294","content_type":"application/pdf","success":1}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["coldboot"],"type":"conference","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/FPT.2013.6718394","author":[{"id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler"},{"full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias","id":"3145"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","year":"2013","date_updated":"2023-09-26T13:37:35Z","citation":{"bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2013:386-389. doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2013, pp. 386–89, doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–89. IEEE, 2013. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2013, pp. 386–389, doi: <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","apa":"Riebler, H., Kenter, T., Sorge, C., &#38; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–389. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>"},"file_date_updated":"2018-03-15T10:36:08Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","publisher":"IEEE","_id":"528","page":"386-389","user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1"},{"abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","type":"conference","department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"date_created":"2018-03-15T13:38:56Z","creator":"florida","file_id":"1308","content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T13:38:56Z","file_name":"505-Plessl13_seus.pdf","access_level":"closed","file_size":1040834}],"date_created":"2017-10-17T12:42:30Z","date_updated":"2023-09-26T13:38:20Z","year":"2013","title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"full_name":"Kling, Peter","first_name":"Peter","last_name":"Kling"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"id":"15523","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide","first_name":"Friedhelm"}],"doi":"10.1109/ISORC.2013.6913232","language":[{"iso":"eng"}],"quality_controlled":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"file_date_updated":"2018-03-15T13:38:56Z","citation":{"ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>, IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE, 2013. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>.","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., &#38; Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>."},"has_accepted_license":"1","status":"public","user_id":"15278","ddc":["040"],"_id":"505","publisher":"IEEE"},{"language":[{"iso":"eng"}],"_id":"1787","publisher":"IEEE Computer Society","page":"64-73","doi":"10.1109/IPDPSW.2013.136","user_id":"15278","publication_identifier":{"isbn":["978-0-7695-4979-8"]},"author":[{"full_name":"Suess, Tim","last_name":"Suess","first_name":"Tim"},{"full_name":"Schoenrock, Andrew","first_name":"Andrew","last_name":"Schoenrock"},{"full_name":"Meisner, Sebastian","last_name":"Meisner","first_name":"Sebastian"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"status":"public","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","year":"2013","date_updated":"2023-09-26T13:38:05Z","place":"Washington, DC, USA","date_created":"2018-03-26T14:51:05Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"type":"conference","citation":{"mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, IEEE Computer Society, 2013, pp. 64–73, doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>. IEEE Computer Society; 2013:64-73. doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 2013, pp. 64–73, doi: <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>.","apa":"Suess, T., Schoenrock, A., Meisner, S., &#38; Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. Washington, DC, USA: IEEE Computer Society, 2013. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>."},"publication":"Proc. Int. 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IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2012.6412125\">https://doi.org/10.1109/FPT.2012.6412125</a>","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={<a href=\"https://doi.org/10.1109/FPT.2012.6412125\">10.1109/FPT.2012.6412125</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2012:135-140. doi:<a href=\"https://doi.org/10.1109/FPT.2012.6412125\">10.1109/FPT.2012.6412125</a>","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” <i>Proc. Int. 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W Jacobson, Physics in Medicine and Biology 57 (2012) 867–883.","ieee":"K. Thielemans <i>et al.</i>, “STIR: Software for Tomographic Image Reconstruction Release 2,” <i>Physics in Medicine and Biology</i>, vol. 57, no. 4, pp. 867–883, 2012.","apa":"Thielemans, K., Tsoumpas, C., Mustafovic, S., Beisel, T., Aguiar, P., Dikaios, N., &#38; W Jacobson, M. (2012). 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Journal of Electronics</i> 100, no. 12 (2012): 1646–51. <a href=\"https://doi.org/10.1080/00207217.2012.751343\">https://doi.org/10.1080/00207217.2012.751343</a>.","short":"S. Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651.","ieee":"S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” <i>Int. Journal of Electronics</i>, vol. 100, no. 12, pp. 1646–1651, 2012.","apa":"Redif, S., &#38; Kasap, S. (2012). Parallel algorithm for computation of second-order sequential best rotations. <i>Int. Journal of Electronics</i>, <i>100</i>(12), 1646–1651. <a href=\"https://doi.org/10.1080/00207217.2012.751343\">https://doi.org/10.1080/00207217.2012.751343</a>","bibtex":"@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={<a href=\"https://doi.org/10.1080/00207217.2012.751343\">10.1080/00207217.2012.751343</a>}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor &#38; Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }","ama":"Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. <i>Int Journal of Electronics</i>. 2012;100(12):1646-1651. doi:<a href=\"https://doi.org/10.1080/00207217.2012.751343\">10.1080/00207217.2012.751343</a>","mla":"Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” <i>Int. Journal of Electronics</i>, vol. 100, no. 12, Taylor &#38; Francis, 2012, pp. 1646–51, doi:<a href=\"https://doi.org/10.1080/00207217.2012.751343\">10.1080/00207217.2012.751343</a>."},"issue":"12","publication":"Int. Journal of Electronics"},{"volume":7,"user_id":"24135","publisher":"Academy Publishers","_id":"2174","page":"1312-1328","intvolume":"         7","date_updated":"2022-01-06T06:55:12Z","author":[{"first_name":"Server","last_name":"Kasap","full_name":"Kasap, Server"},{"last_name":"Benkrid","first_name":"Khaled","full_name":"Benkrid, Khaled"}],"year":"2012","status":"public","title":"Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer","department":[{"_id":"27"},{"_id":"78"}],"type":"journal_article","date_created":"2018-04-03T09:08:00Z","citation":{"mla":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” <i>Journal of Computers</i>, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.","ama":"Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. <i>Journal of Computers</i>. 2012;7(6):1312-1328.","bibtex":"@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }","apa":"Kasap, S., &#38; Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. <i>Journal of Computers</i>, <i>7</i>(6), 1312–1328.","ieee":"S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” <i>Journal of Computers</i>, vol. 7, no. 6, pp. 1312–1328, 2012.","short":"S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328.","chicago":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” <i>Journal of Computers</i> 7, no. 6 (2012): 1312–28."},"issue":"6","publication":"Journal of Computers"},{"department":[{"_id":"78"}],"type":"dissertation","date_created":"2017-10-17T12:42:46Z","file":[{"creator":"florida","date_created":"2018-03-15T08:38:19Z","file_name":"586-Drzevitzky-PhD_01.pdf","access_level":"closed","file_size":1438436,"relation":"main_file","date_updated":"2018-03-15T08:38:19Z","file_id":"1261","success":1,"content_type":"application/pdf"}],"abstract":[{"text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.","lang":"eng"},{"text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit.","lang":"ger"}],"language":[{"iso":"eng"}],"main_file_link":[{"url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423","open_access":"1"}],"publication_status":"published","date_updated":"2022-01-06T07:02:44Z","author":[{"first_name":"Stephanie","last_name":"Drzevitzky","full_name":"Drzevitzky, Stephanie"}],"title":"Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security","year":"2012","oa":"1","project":[{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"}],"citation":{"mla":"Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","ama":"Drzevitzky S. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn; 2012.","bibtex":"@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }","apa":"Drzevitzky, S. (2012). <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn.","ieee":"S. Drzevitzky, <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","chicago":"Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","short":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security, Universität Paderborn, 2012."},"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"file_date_updated":"2018-03-15T08:38:19Z","user_id":"477","ddc":["040"],"_id":"586","publisher":"Universität Paderborn","page":"114","has_accepted_license":"1","status":"public"},{"type":"misc","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"relation":"main_file","date_updated":"2018-03-15T08:37:02Z","file_name":"587-2012_plessl_awareness_magazine.pdf","access_level":"closed","file_size":353057,"file_id":"1260","success":1,"content_type":"application/pdf","creator":"florida","date_created":"2018-03-15T08:37:02Z"}],"date_created":"2017-10-17T12:42:46Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"file_date_updated":"2018-03-15T08:37:02Z","citation":{"short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012.","chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine, 2012.","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., &#38; Lübbers, E. (2012). <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine; 2012.","mla":"Plessl, Christian, et al. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012."},"ddc":["040"],"user_id":"398","_id":"587","publisher":"Awareness Magazine","language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:02:44Z","has_accepted_license":"1","year":"2012","status":"public","title":"Programming models for reconfigurable heterogeneous multi-cores","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"}]},{"user_id":"3118","language":[{"iso":"eng"}],"_id":"10636","date_updated":"2022-01-06T06:50:49Z","year":"2012","status":"public","title":"Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array","author":[{"first_name":"Alexander","last_name":"Boschmann","full_name":"Boschmann, Alexander"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T11:03:21Z","publication":"Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)","citation":{"ieee":"A. Boschmann and M. Platzner, “Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array,” in <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2012.","mla":"Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode Shift Using a High Density Electrode Array.” <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2012.","apa":"Boschmann, A., &#38; Platzner, M. (2012). Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>.","bibtex":"@inproceedings{Boschmann_Platzner_2012, title={Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2012} }","ama":"Boschmann A, Platzner M. Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In: <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>. ; 2012.","short":"A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012.","chicago":"Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode Shift Using a High Density Electrode Array.” In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2012."}},{"user_id":"3118","_id":"10650","language":[{"iso":"eng"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","status":"public","title":"Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer","year":"2012","author":[{"first_name":"Denis","last_name":"Dridger","full_name":"Dridger, Denis"}],"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T11:10:59Z","citation":{"ieee":"D. Dridger, <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","apa":"Dridger, D. (2012). <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University.","chicago":"Dridger, Denis. <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","short":"D. Dridger, Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer, Paderborn University, 2012.","mla":"Dridger, Denis. <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","bibtex":"@book{Dridger_2012, title={Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Dridger, Denis}, year={2012} }","ama":"Dridger D. <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University; 2012."}},{"abstract":[{"lang":"eng","text":"The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores."}],"supervisor":[{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"citation":{"short":"H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores, Logos Verlag Berlin GmbH, Berlin, 2012.","chicago":"Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2012.","ieee":"H. Giefers, <i>Design and Programming of Reconfigurable Mesh based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2012.","apa":"Giefers, H. (2012). <i>Design and Programming of Reconfigurable Mesh based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH.","bibtex":"@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }","ama":"Giefers H. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH; 2012.","mla":"Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Logos Verlag Berlin GmbH, 2012."},"department":[{"_id":"78"}],"type":"dissertation","place":"Berlin","date_created":"2019-07-10T11:13:12Z","date_updated":"2022-01-06T06:50:49Z","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3165-2"]},"author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"}],"status":"public","title":"Design and Programming of Reconfigurable Mesh based Many-Cores","year":"2012","user_id":"3118","_id":"10652","language":[{"iso":"eng"}],"publisher":"Logos Verlag Berlin GmbH","page":"159"},{"author":[{"last_name":"Graf","first_name":"Tobias","full_name":"Graf, Tobias"}],"title":"Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go","status":"public","year":"2012","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"_id":"10658","publisher":"Paderborn University","user_id":"3118","supervisor":[{"full_name":"Schäfers, Lars","first_name":"Lars","last_name":"Schäfers"}],"citation":{"bibtex":"@book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias}, year={2012} }","ama":"Graf T. <i>Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go</i>. Paderborn University; 2012.","mla":"Graf, Tobias. <i>Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go</i>. Paderborn University, 2012.","short":"T. Graf, Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go, Paderborn University, 2012.","chicago":"Graf, Tobias. <i>Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go</i>. Paderborn University, 2012.","ieee":"T. Graf, <i>Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go</i>. Paderborn University, 2012.","apa":"Graf, T. (2012). <i>Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go</i>. Paderborn University."},"date_created":"2019-07-10T11:13:34Z","department":[{"_id":"78"}],"type":"mastersthesis"},{"date_created":"2019-07-10T11:15:12Z","department":[{"_id":"78"}],"type":"bachelorsthesis","supervisor":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"}],"citation":{"ieee":"H. Hangmann, <i>Generating Adjustable Temperature Gradients on modern FPGAs</i>. Paderborn University, 2012.","apa":"Hangmann, H. (2012). <i>Generating Adjustable Temperature Gradients on modern FPGAs</i>. Paderborn University.","chicago":"Hangmann, Hendrik. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Paderborn University, 2012.","short":"H. Hangmann, Generating Adjustable Temperature Gradients on Modern FPGAs, Paderborn University, 2012.","mla":"Hangmann, Hendrik. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Paderborn University, 2012.","bibtex":"@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2012} }","ama":"Hangmann H. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Paderborn University; 2012."},"language":[{"iso":"eng"}],"_id":"10667","publisher":"Paderborn University","user_id":"3118","author":[{"last_name":"Hangmann","first_name":"Hendrik","full_name":"Hangmann, Hendrik"}],"title":"Generating Adjustable Temperature Gradients on modern FPGAs","year":"2012","status":"public","date_updated":"2022-01-06T06:50:49Z"},{"year":"2012","status":"public","title":"Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture","author":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"last_name":"Glette","first_name":"Kyrre","full_name":"Glette, Kyrre"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Jim","last_name":"Torresen","full_name":"Torresen, Jim"}],"date_updated":"2022-01-06T06:50:49Z","intvolume":"         3","page":"17-31","language":[{"iso":"eng"}],"_id":"10685","publisher":"IGI Global","doi":"10.4018/jaras.2012100102","user_id":"3118","volume":3,"publication":"International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)","issue":"4","citation":{"mla":"Kaufmann, Paul, et al. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>, vol. 3, no. 4, IGI Global, 2012, pp. 17–31, doi:<a href=\"https://doi.org/10.4018/jaras.2012100102\">10.4018/jaras.2012100102</a>.","ama":"Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>. 2012;3(4):17-31. doi:<a href=\"https://doi.org/10.4018/jaras.2012100102\">10.4018/jaras.2012100102</a>","bibtex":"@article{Kaufmann_Glette_Platzner_Torresen_2012, title={Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}, volume={3}, DOI={<a href=\"https://doi.org/10.4018/jaras.2012100102\">10.4018/jaras.2012100102</a>}, number={4}, journal={International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}, publisher={IGI Global}, author={Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2012}, pages={17–31} }","apa":"Kaufmann, P., Glette, K., Platzner, M., &#38; Torresen, J. (2012). Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>, <i>3</i>(4), 17–31. <a href=\"https://doi.org/10.4018/jaras.2012100102\">https://doi.org/10.4018/jaras.2012100102</a>","ieee":"P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture,” <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>, vol. 3, no. 4, pp. 17–31, 2012.","chicago":"Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i> 3, no. 4 (2012): 17–31. <a href=\"https://doi.org/10.4018/jaras.2012100102\">https://doi.org/10.4018/jaras.2012100102</a>.","short":"P. Kaufmann, K. Glette, M. Platzner, J. Torresen, International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3 (2012) 17–31."},"date_created":"2019-07-10T11:28:10Z","type":"journal_article","department":[{"_id":"78"}]}]