[{"file":[{"file_name":"586-Drzevitzky-PhD_01.pdf","file_id":"1261","access_level":"closed","file_size":1438436,"creator":"florida","date_created":"2018-03-15T08:38:19Z","date_updated":"2018-03-15T08:38:19Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"abstract":[{"text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.","lang":"eng"},{"lang":"ger","text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit."}],"language":[{"iso":"eng"}],"ddc":["040"],"year":"2012","title":"Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security","date_created":"2017-10-17T12:42:46Z","publisher":"Universität Paderborn","status":"public","type":"dissertation","file_date_updated":"2018-03-15T08:38:19Z","department":[{"_id":"78"}],"user_id":"477","_id":"586","project":[{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"page":"114","citation":{"mla":"Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","bibtex":"@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }","short":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security, Universität Paderborn, 2012.","apa":"Drzevitzky, S. (2012). <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn.","chicago":"Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","ieee":"S. Drzevitzky, <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","ama":"Drzevitzky S. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn; 2012."},"has_accepted_license":"1","publication_status":"published","main_file_link":[{"url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423","open_access":"1"}],"author":[{"first_name":"Stephanie","last_name":"Drzevitzky","full_name":"Drzevitzky, Stephanie"}],"supervisor":[{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"oa":"1","date_updated":"2022-01-06T07:02:44Z"},{"has_accepted_license":"1","citation":{"chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine, 2012.","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine; 2012.","mla":"Plessl, Christian, et al. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., &#38; Lübbers, E. (2012). <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine."},"year":"2012","date_created":"2017-10-17T12:42:46Z","author":[{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"}],"date_updated":"2022-01-06T07:02:44Z","publisher":"Awareness Magazine","title":"Programming models for reconfigurable heterogeneous multi-cores","type":"misc","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":353057,"access_level":"closed","file_name":"587-2012_plessl_awareness_magazine.pdf","file_id":"1260","date_updated":"2018-03-15T08:37:02Z","creator":"florida","date_created":"2018-03-15T08:37:02Z"}],"status":"public","user_id":"398","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"_id":"587","file_date_updated":"2018-03-15T08:37:02Z","language":[{"iso":"eng"}],"ddc":["040"]},{"citation":{"ama":"Boschmann A, Platzner M. Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In: <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>. ; 2012.","chicago":"Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode Shift Using a High Density Electrode Array.” In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2012.","ieee":"A. Boschmann and M. Platzner, “Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array,” in <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2012.","apa":"Boschmann, A., &#38; Platzner, M. (2012). Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>.","mla":"Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode Shift Using a High Density Electrode Array.” <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2012.","bibtex":"@inproceedings{Boschmann_Platzner_2012, title={Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2012} }","short":"A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012."},"year":"2012","title":"Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array","author":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2019-07-10T11:03:21Z","date_updated":"2022-01-06T06:50:49Z","status":"public","type":"conference","publication":"Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)","language":[{"iso":"eng"}],"user_id":"3118","department":[{"_id":"78"}],"_id":"10636"},{"citation":{"short":"D. Dridger, Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer, Paderborn University, 2012.","bibtex":"@book{Dridger_2012, title={Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Dridger, Denis}, year={2012} }","mla":"Dridger, Denis. <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","apa":"Dridger, D. (2012). <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University.","ama":"Dridger D. <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University; 2012.","chicago":"Dridger, Denis. <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","ieee":"D. Dridger, <i>Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer</i>. Paderborn University, 2012."},"year":"2012","date_created":"2019-07-10T11:10:59Z","author":[{"full_name":"Dridger, Denis","last_name":"Dridger","first_name":"Denis"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","title":"Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer","type":"mastersthesis","status":"public","user_id":"3118","department":[{"_id":"78"}],"_id":"10650","language":[{"iso":"eng"}]},{"supervisor":[{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2019-07-10T11:13:12Z","author":[{"full_name":"Giefers, Heiner","last_name":"Giefers","first_name":"Heiner"}],"date_updated":"2022-01-06T06:50:49Z","publisher":"Logos Verlag Berlin GmbH","title":"Design and Programming of Reconfigurable Mesh based Many-Cores","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3165-2"]},"citation":{"mla":"Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Logos Verlag Berlin GmbH, 2012.","bibtex":"@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }","short":"H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores, Logos Verlag Berlin GmbH, Berlin, 2012.","apa":"Giefers, H. (2012). <i>Design and Programming of Reconfigurable Mesh based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH.","ama":"Giefers H. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH; 2012.","ieee":"H. Giefers, <i>Design and Programming of Reconfigurable Mesh based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2012.","chicago":"Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2012."},"page":"159","year":"2012","place":"Berlin","user_id":"3118","department":[{"_id":"78"}],"_id":"10652","language":[{"iso":"eng"}],"type":"dissertation","status":"public","abstract":[{"lang":"eng","text":"The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores."}]},{"department":[{"_id":"78"}],"user_id":"3118","_id":"10658","language":[{"iso":"eng"}],"type":"mastersthesis","status":"public","supervisor":[{"first_name":"Lars","last_name":"Schäfers","full_name":"Schäfers, Lars"}],"date_created":"2019-07-10T11:13:34Z","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"}],"date_updated":"2022-01-06T06:50:49Z","publisher":"Paderborn University","title":"Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go","citation":{"ieee":"T. Graf, <i>Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go</i>. Paderborn University, 2012.","chicago":"Graf, Tobias. <i>Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go</i>. Paderborn University, 2012.","ama":"Graf T. <i>Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go</i>. Paderborn University; 2012.","mla":"Graf, Tobias. <i>Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go</i>. Paderborn University, 2012.","bibtex":"@book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias}, year={2012} }","short":"T. Graf, Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go, Paderborn University, 2012.","apa":"Graf, T. (2012). <i>Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go</i>. Paderborn University."},"year":"2012"},{"title":"Generating Adjustable Temperature Gradients on modern FPGAs","date_updated":"2022-01-06T06:50:49Z","publisher":"Paderborn University","supervisor":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"}],"author":[{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"}],"date_created":"2019-07-10T11:15:12Z","year":"2012","citation":{"ieee":"H. Hangmann, <i>Generating Adjustable Temperature Gradients on modern FPGAs</i>. Paderborn University, 2012.","chicago":"Hangmann, Hendrik. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Paderborn University, 2012.","ama":"Hangmann H. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Paderborn University; 2012.","bibtex":"@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2012} }","short":"H. Hangmann, Generating Adjustable Temperature Gradients on Modern FPGAs, Paderborn University, 2012.","mla":"Hangmann, Hendrik. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Paderborn University, 2012.","apa":"Hangmann, H. (2012). <i>Generating Adjustable Temperature Gradients on modern FPGAs</i>. Paderborn University."},"language":[{"iso":"eng"}],"_id":"10667","department":[{"_id":"78"}],"user_id":"3118","status":"public","type":"bachelorsthesis"},{"department":[{"_id":"78"}],"user_id":"3118","_id":"10685","language":[{"iso":"eng"}],"publication":"International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)","type":"journal_article","status":"public","volume":3,"date_created":"2019-07-10T11:28:10Z","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Torresen","full_name":"Torresen, Jim","first_name":"Jim"}],"date_updated":"2022-01-06T06:50:49Z","publisher":"IGI Global","doi":"10.4018/jaras.2012100102","title":"Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture","issue":"4","intvolume":"         3","page":"17-31","citation":{"mla":"Kaufmann, Paul, et al. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>, vol. 3, no. 4, IGI Global, 2012, pp. 17–31, doi:<a href=\"https://doi.org/10.4018/jaras.2012100102\">10.4018/jaras.2012100102</a>.","bibtex":"@article{Kaufmann_Glette_Platzner_Torresen_2012, title={Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}, volume={3}, DOI={<a href=\"https://doi.org/10.4018/jaras.2012100102\">10.4018/jaras.2012100102</a>}, number={4}, journal={International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}, publisher={IGI Global}, author={Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2012}, pages={17–31} }","short":"P. Kaufmann, K. Glette, M. Platzner, J. Torresen, International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3 (2012) 17–31.","apa":"Kaufmann, P., Glette, K., Platzner, M., &#38; Torresen, J. (2012). Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>, <i>3</i>(4), 17–31. <a href=\"https://doi.org/10.4018/jaras.2012100102\">https://doi.org/10.4018/jaras.2012100102</a>","ieee":"P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture,” <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>, vol. 3, no. 4, pp. 17–31, 2012.","chicago":"Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i> 3, no. 4 (2012): 17–31. <a href=\"https://doi.org/10.4018/jaras.2012100102\">https://doi.org/10.4018/jaras.2012100102</a>.","ama":"Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. <i>International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)</i>. 2012;3(4):17-31. doi:<a href=\"https://doi.org/10.4018/jaras.2012100102\">10.4018/jaras.2012100102</a>"},"year":"2012"},{"year":"2012","citation":{"ama":"Platzner M, Boschmann A, Kaufmann P. <i>Wieder Natürlich Gehen Und Greifen</i>.; 2012:6-11.","ieee":"M. Platzner, A. Boschmann, and P. Kaufmann, <i>Wieder natürlich gehen und greifen</i>. 2012, pp. 6–11.","chicago":"Platzner, Marco, Alexander Boschmann, and Paul Kaufmann. <i>Wieder Natürlich Gehen Und Greifen</i>, 2012.","mla":"Platzner, Marco, et al. <i>Wieder Natürlich Gehen Und Greifen</i>. 2012, pp. 6–11.","bibtex":"@book{Platzner_Boschmann_Kaufmann_2012, title={Wieder natürlich gehen und greifen}, author={Platzner, Marco and Boschmann, Alexander and Kaufmann, Paul}, year={2012}, pages={6–11} }","short":"M. Platzner, A. Boschmann, P. Kaufmann, Wieder Natürlich Gehen Und Greifen, 2012.","apa":"Platzner, M., Boschmann, A., &#38; Kaufmann, P. (2012). <i>Wieder natürlich gehen und greifen</i> (pp. 6–11)."},"page":"6-11","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T11:54:15Z","author":[{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"}],"title":"Wieder natürlich gehen und greifen","type":"misc","status":"public","_id":"10723","user_id":"398","department":[{"_id":"78"}],"language":[{"iso":"eng"}]},{"year":"2012","citation":{"ama":"Schmitz H. <i>Stereo Matching on a HC-1 Hybrid Core Computer</i>. Paderborn University; 2012.","chicago":"Schmitz, Henning. <i>Stereo Matching on a HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","ieee":"H. Schmitz, <i>Stereo Matching on a HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","mla":"Schmitz, Henning. <i>Stereo Matching on a HC-1 Hybrid Core Computer</i>. Paderborn University, 2012.","bibtex":"@book{Schmitz_2012, title={Stereo Matching on a HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Schmitz, Henning}, year={2012} }","short":"H. Schmitz, Stereo Matching on a HC-1 Hybrid Core Computer, Paderborn University, 2012.","apa":"Schmitz, H. (2012). <i>Stereo Matching on a HC-1 Hybrid Core Computer</i>. Paderborn University."},"title":"Stereo Matching on a HC-1 Hybrid Core Computer","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Schmitz","full_name":"Schmitz, Henning","first_name":"Henning"}],"date_created":"2019-07-10T11:58:08Z","status":"public","type":"bachelorsthesis","language":[{"iso":"eng"}],"_id":"10734","department":[{"_id":"78"}],"user_id":"3118"},{"type":"bachelorsthesis","status":"public","_id":"10747","department":[{"_id":"78"}],"user_id":"3118","language":[{"iso":"eng"}],"year":"2012","citation":{"ama":"Topmöller C. <i>Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System</i>. Paderborn University; 2012.","chicago":"Topmöller, Christoph. <i>Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System</i>. Paderborn University, 2012.","ieee":"C. Topmöller, <i>Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System</i>. Paderborn University, 2012.","bibtex":"@book{Topmöller_2012, title={Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}, publisher={Paderborn University}, author={Topmöller, Christoph}, year={2012} }","mla":"Topmöller, Christoph. <i>Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System</i>. Paderborn University, 2012.","short":"C. Topmöller, Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System, Paderborn University, 2012.","apa":"Topmöller, C. (2012). <i>Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System</i>. Paderborn University."},"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Topmöller","full_name":"Topmöller, Christoph","first_name":"Christoph"}],"date_created":"2019-07-10T12:01:53Z","title":"Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System"},{"title":"Analysis of Pattern Based Model Design and Learning in Computer-Go","author":[{"first_name":"Martin","last_name":"Wistuba","full_name":"Wistuba, Martin"}],"date_created":"2019-07-10T12:05:19Z","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","citation":{"ieee":"M. Wistuba, <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University, 2012.","chicago":"Wistuba, Martin. <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University, 2012.","ama":"Wistuba M. <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University; 2012.","apa":"Wistuba, M. (2012). <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University.","short":"M. Wistuba, Analysis of Pattern Based Model Design and Learning in Computer-Go, Paderborn University, 2012.","bibtex":"@book{Wistuba_2012, title={Analysis of Pattern Based Model Design and Learning in Computer-Go}, publisher={Paderborn University}, author={Wistuba, Martin}, year={2012} }","mla":"Wistuba, Martin. <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University, 2012."},"year":"2012","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"3118","_id":"10754","status":"public","type":"mastersthesis"},{"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"_id":"13462","user_id":"398","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"misc","status":"public","publisher":"Awareness Magazine","date_updated":"2022-01-06T06:51:36Z","date_created":"2019-09-30T09:24:09Z","author":[{"last_name":"Lewis","full_name":"Lewis, Peter","first_name":"Peter"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"},{"last_name":"Yao","full_name":"Yao, Xin","first_name":"Xin"}],"title":"An outlook for self-awareness in computing systems","year":"2012","citation":{"ama":"Lewis P, Platzner M, Yao X. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine; 2012.","ieee":"P. Lewis, M. Platzner, and X. Yao, <i>An outlook for self-awareness in computing systems</i>. Awareness Magazine, 2012.","chicago":"Lewis, Peter, Marco Platzner, and Xin Yao. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine, 2012.","mla":"Lewis, Peter, et al. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine, 2012.","short":"P. Lewis, M. Platzner, X. Yao, An Outlook for Self-Awareness in Computing Systems, Awareness Magazine, 2012.","bibtex":"@book{Lewis_Platzner_Yao_2012, title={An outlook for self-awareness in computing systems}, publisher={Awareness Magazine}, author={Lewis, Peter and Platzner, Marco and Yao, Xin}, year={2012} }","apa":"Lewis, P., Platzner, M., &#38; Yao, X. (2012). <i>An outlook for self-awareness in computing systems</i>. Awareness Magazine."}},{"conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","author":[{"full_name":"Meyer, Björn","last_name":"Meyer","first_name":"Björn"},{"first_name":"Jörn","last_name":"Schumacher","full_name":"Schumacher, Jörn"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner","full_name":"Förstner, Jens","id":"158"}],"citation":{"ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:189-196. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 189–196, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–96. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","apa":"Meyer, B., Schumacher, J., Plessl, C., &#38; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–196. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 189–96, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>."},"page":"189-196","has_accepted_license":"1","file_date_updated":"2019-02-13T09:04:46Z","_id":"2106","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"status":"public","type":"conference","title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","publisher":"IEEE","date_created":"2018-03-29T15:04:25Z","year":"2012","quality_controlled":"1","ddc":["000"],"keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"file":[{"date_updated":"2019-02-13T09:04:46Z","date_created":"2019-02-13T09:04:46Z","creator":"fossie","file_size":2148787,"access_level":"closed","file_id":"7638","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","content_type":"application/pdf","success":1,"relation":"main_file"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)"},{"year":"2012","page":"110-126","intvolume":"        36","citation":{"bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, 2012, pp. 110–26, doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>, <i>36</i>(2), 110–126. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>. 2012;36(2):110-126. doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, pp. 110–126, 2012, doi: <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i> 36, no. 2 (2012): 110–26. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>."},"publication_identifier":{"issn":["0141-9331"]},"quality_controlled":"1","issue":"2","title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","volume":36,"author":[{"full_name":"Schumacher, Tobias","last_name":"Schumacher","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_created":"2018-03-29T15:12:38Z","status":"public","publication":"Microprocessors and Microsystems","type":"journal_article","keyword":["funding-altera"],"language":[{"iso":"eng"}],"_id":"2108","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278"},{"has_accepted_license":"1","page":"1-8","citation":{"chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","apa":"Happe, M., Hangmann, H., Agne, A., &#38; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>"},"date_updated":"2023-09-26T13:42:26Z","author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"doi":"10.1109/ReConFig.2012.6416745","type":"conference","status":"public","_id":"615","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","file_date_updated":"2018-03-15T06:48:32Z","quality_controlled":"1","year":"2012","publisher":"IEEE","date_created":"2017-10-17T12:42:51Z","title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.","lang":"eng"}],"file":[{"file_size":730144,"access_level":"closed","file_id":"1246","file_name":"615-ReConFig12_01.pdf","date_updated":"2018-03-15T06:48:32Z","creator":"florida","date_created":"2018-03-15T06:48:32Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"ddc":["040"],"language":[{"iso":"eng"}]},{"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"file":[{"file_size":371235,"access_level":"closed","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","file_id":"1257","date_updated":"2018-03-15T08:33:18Z","creator":"florida","date_created":"2018-03-15T08:33:18Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","ddc":["040"],"language":[{"iso":"eng"}],"year":"2012","quality_controlled":"1","title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","publisher":"IEEE","date_created":"2017-10-17T12:42:47Z","status":"public","type":"conference","file_date_updated":"2018-03-15T08:33:18Z","_id":"591","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","page":"1-8","citation":{"ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>."},"has_accepted_license":"1","doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","author":[{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"last_name":"Schmitz","full_name":"Schmitz, Henning","first_name":"Henning"}]},{"title":"Hardware/Software Platform for Self-aware Compute Nodes","date_updated":"2023-09-26T13:41:36Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"date_created":"2017-10-17T12:42:50Z","year":"2012","citation":{"apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012."},"page":"8-9","quality_controlled":"1","has_accepted_license":"1","ddc":["040"],"file_date_updated":"2018-03-15T08:14:17Z","language":[{"iso":"eng"}],"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"609","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_name":"609-happe12_fpl_awareness.pdf","access_level":"closed","file_id":"1249","file_size":146789,"creator":"florida","date_created":"2018-03-15T08:14:17Z","date_updated":"2018-03-15T08:14:17Z"}],"status":"public","type":"conference","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)"},{"page":"559-565","citation":{"chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>."},"has_accepted_license":"1","doi":"10.1109/HPCSim.2012.6266973","date_updated":"2023-09-26T13:42:54Z","author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"first_name":"Carlos","last_name":"Carreras","full_name":"Carreras, Carlos"},{"first_name":"Roberto","last_name":"Sierra","full_name":"Sierra, Roberto"},{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"status":"public","type":"conference","file_date_updated":"2018-03-15T10:20:24Z","_id":"567","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","year":"2012","quality_controlled":"1","title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","publisher":"IEEE","date_created":"2017-10-17T12:42:42Z","abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided."}],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2018-03-15T10:20:24Z","creator":"florida","date_updated":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","file_id":"1275","access_level":"closed","file_size":288508}],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","ddc":["040"],"language":[{"iso":"eng"}]},{"abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"file":[{"file_id":"1247","access_level":"closed","file_name":"612-ruething_fpl12.pdf","file_size":202923,"date_created":"2018-03-15T06:49:03Z","creator":"florida","date_updated":"2018-03-15T06:49:03Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"status":"public","type":"conference","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","ddc":["040"],"file_date_updated":"2018-03-15T06:49:03Z","language":[{"iso":"eng"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"_id":"612","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"year":"2012","citation":{"ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }"},"page":"559-562","quality_controlled":"1","has_accepted_license":"1","title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:42:03Z","publisher":"IEEE","author":[{"last_name":"Rüthing","full_name":"Rüthing, Christoph","first_name":"Christoph"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"date_created":"2017-10-17T12:42:51Z"}]