[{"citation":{"ama":"Topmöller C. <i>Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System</i>. Paderborn University; 2012.","ieee":"C. Topmöller, <i>Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System</i>. Paderborn University, 2012.","chicago":"Topmöller, Christoph. <i>Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System</i>. Paderborn University, 2012.","apa":"Topmöller, C. (2012). <i>Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System</i>. Paderborn University.","bibtex":"@book{Topmöller_2012, title={Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}, publisher={Paderborn University}, author={Topmöller, Christoph}, year={2012} }","mla":"Topmöller, Christoph. <i>Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System</i>. Paderborn University, 2012.","short":"C. Topmöller, Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System, Paderborn University, 2012."},"year":"2012","title":"Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System","date_created":"2019-07-10T12:01:53Z","author":[{"full_name":"Topmöller, Christoph","last_name":"Topmöller","first_name":"Christoph"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","status":"public","type":"bachelorsthesis","language":[{"iso":"eng"}],"user_id":"3118","department":[{"_id":"78"}],"_id":"10747"},{"type":"mastersthesis","status":"public","_id":"10754","user_id":"3118","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"year":"2012","citation":{"ama":"Wistuba M. <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University; 2012.","ieee":"M. Wistuba, <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University, 2012.","chicago":"Wistuba, Martin. <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University, 2012.","apa":"Wistuba, M. (2012). <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University.","bibtex":"@book{Wistuba_2012, title={Analysis of Pattern Based Model Design and Learning in Computer-Go}, publisher={Paderborn University}, author={Wistuba, Martin}, year={2012} }","mla":"Wistuba, Martin. <i>Analysis of Pattern Based Model Design and Learning in Computer-Go</i>. Paderborn University, 2012.","short":"M. Wistuba, Analysis of Pattern Based Model Design and Learning in Computer-Go, Paderborn University, 2012."},"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","author":[{"first_name":"Martin","full_name":"Wistuba, Martin","last_name":"Wistuba"}],"date_created":"2019-07-10T12:05:19Z","title":"Analysis of Pattern Based Model Design and Learning in Computer-Go"},{"author":[{"first_name":"Peter","last_name":"Lewis","full_name":"Lewis, Peter"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"},{"last_name":"Yao","full_name":"Yao, Xin","first_name":"Xin"}],"date_created":"2019-09-30T09:24:09Z","publisher":"Awareness Magazine","date_updated":"2022-01-06T06:51:36Z","title":"An outlook for self-awareness in computing systems","citation":{"mla":"Lewis, Peter, et al. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine, 2012.","short":"P. Lewis, M. Platzner, X. Yao, An Outlook for Self-Awareness in Computing Systems, Awareness Magazine, 2012.","bibtex":"@book{Lewis_Platzner_Yao_2012, title={An outlook for self-awareness in computing systems}, publisher={Awareness Magazine}, author={Lewis, Peter and Platzner, Marco and Yao, Xin}, year={2012} }","apa":"Lewis, P., Platzner, M., &#38; Yao, X. (2012). <i>An outlook for self-awareness in computing systems</i>. Awareness Magazine.","ama":"Lewis P, Platzner M, Yao X. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine; 2012.","chicago":"Lewis, Peter, Marco Platzner, and Xin Yao. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine, 2012.","ieee":"P. Lewis, M. Platzner, and X. Yao, <i>An outlook for self-awareness in computing systems</i>. Awareness Magazine, 2012."},"year":"2012","user_id":"398","department":[{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"_id":"13462","language":[{"iso":"eng"}],"type":"misc","status":"public"},{"status":"public","type":"conference","file_date_updated":"2019-02-13T09:04:46Z","_id":"2106","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"user_id":"15278","page":"189-196","citation":{"chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–96. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 189–196, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:189-196. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","apa":"Meyer, B., Schumacher, J., Plessl, C., &#38; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–196. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 189–96, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196."},"has_accepted_license":"1","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","author":[{"full_name":"Meyer, Björn","last_name":"Meyer","first_name":"Björn"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner"}],"abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2019-02-13T09:04:46Z","creator":"fossie","date_updated":"2019-02-13T09:04:46Z","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","file_id":"7638","access_level":"closed","file_size":2148787}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"ddc":["000"],"language":[{"iso":"eng"}],"year":"2012","quality_controlled":"1","title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","publisher":"IEEE","date_created":"2018-03-29T15:04:25Z"},{"volume":36,"author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2018-03-29T15:12:38Z","date_updated":"2023-09-26T13:39:30Z","doi":"10.1016/j.micpro.2011.04.002","title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","issue":"2","publication_identifier":{"issn":["0141-9331"]},"quality_controlled":"1","page":"110-126","intvolume":"        36","citation":{"short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, 2012, pp. 110–26, doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>, <i>36</i>(2), 110–126. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, pp. 110–126, 2012, doi: <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i> 36, no. 2 (2012): 110–26. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>. 2012;36(2):110-126. doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>"},"year":"2012","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2108","language":[{"iso":"eng"}],"keyword":["funding-altera"],"publication":"Microprocessors and Microsystems","type":"journal_article","status":"public"},{"doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"citation":{"ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>.","apa":"Happe, M., Hangmann, H., Agne, A., &#38; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8."},"page":"1-8","has_accepted_license":"1","file_date_updated":"2018-03-15T06:48:32Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"615","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"conference","title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","publisher":"IEEE","date_created":"2017-10-17T12:42:51Z","year":"2012","quality_controlled":"1","ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"file":[{"date_updated":"2018-03-15T06:48:32Z","date_created":"2018-03-15T06:48:32Z","creator":"florida","file_size":730144,"access_level":"closed","file_name":"615-ReConFig12_01.pdf","file_id":"1246","content_type":"application/pdf","success":1,"relation":"main_file"}],"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)"},{"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"591","file_date_updated":"2018-03-15T08:33:18Z","type":"conference","status":"public","author":[{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"}],"date_updated":"2023-09-26T13:41:08Z","doi":"10.1109/ReConFig.2012.6416773","has_accepted_license":"1","citation":{"short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>"},"page":"1-8","language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":371235,"file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","access_level":"closed","file_id":"1257","date_updated":"2018-03-15T08:33:18Z","creator":"florida","date_created":"2018-03-15T08:33:18Z"}],"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"date_created":"2017-10-17T12:42:47Z","publisher":"IEEE","title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","quality_controlled":"1","year":"2012"},{"year":"2012","citation":{"ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9."},"page":"8-9","has_accepted_license":"1","quality_controlled":"1","title":"Hardware/Software Platform for Self-aware Compute Nodes","date_updated":"2023-09-26T13:41:36Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2017-10-17T12:42:50Z","abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}],"file":[{"file_size":146789,"file_id":"1249","access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf","date_updated":"2018-03-15T08:14:17Z","creator":"florida","date_created":"2018-03-15T08:14:17Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"status":"public","type":"conference","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T08:14:17Z","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"609","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"567","file_date_updated":"2018-03-15T10:20:24Z","type":"conference","status":"public","author":[{"first_name":"Pablo","last_name":"Barrio","full_name":"Barrio, Pablo"},{"full_name":"Carreras, Carlos","last_name":"Carreras","first_name":"Carlos"},{"last_name":"Sierra","full_name":"Sierra, Roberto","first_name":"Roberto"},{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","has_accepted_license":"1","citation":{"apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>"},"page":"559-565","language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file":[{"date_created":"2018-03-15T10:20:24Z","creator":"florida","date_updated":"2018-03-15T10:20:24Z","file_id":"1275","access_level":"closed","file_name":"567-ba-ca-12a.pdf","file_size":288508,"content_type":"application/pdf","relation":"main_file","success":1}],"abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided."}],"date_created":"2017-10-17T12:42:42Z","publisher":"IEEE","title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","quality_controlled":"1","year":"2012"},{"type":"conference","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file":[{"date_created":"2018-03-15T06:49:03Z","creator":"florida","date_updated":"2018-03-15T06:49:03Z","access_level":"closed","file_id":"1247","file_name":"612-ruething_fpl12.pdf","file_size":202923,"content_type":"application/pdf","relation":"main_file","success":1}],"status":"public","abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"_id":"612","language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T06:49:03Z","ddc":["040"],"quality_controlled":"1","has_accepted_license":"1","citation":{"apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. 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Estimation and Partitioning for CPU-Accelerator Architectures. In <i>Intel European Research and Innovation Conference</i>.","short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” <i>Intel European Research and Innovation Conference</i>, 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: <i>Intel European Research and Innovation Conference</i>. ; 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In <i>Intel European Research and Innovation Conference</i>, 2011.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in <i>Intel European Research and Innovation Conference</i>, 2011."}},{"publication_identifier":{"isbn":["978-1-60960-086-0"]},"citation":{"ieee":"C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.","chicago":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” In <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch. Hershey, PA, USA: IGI Global, 2011. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>.","ama":"Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global; 2011. doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>","short":"C. Plessl, M. Platzner, in: M. Khalgui, H.-M. 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Berlin / Heidelberg: Springer, 2011. <a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">https://doi.org/10.1007/978-3-642-23397-5_36</a>.","ieee":"T. Graf, U. Lorenz, M. Platzner, and L. Schaefers, “Parallel Monte-Carlo Tree Search for HPC Systems,” in <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i>, 2011, vol. 6853.","mla":"Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.” <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i>, vol. 6853, Springer, 2011, doi:<a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">10.1007/978-3-642-23397-5_36</a>.","short":"T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, Berlin / Heidelberg, 2011.","bibtex":"@inproceedings{Graf_Lorenz_Platzner_Schaefers_2011, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={Parallel Monte-Carlo Tree Search for HPC Systems}, volume={6853}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">10.1007/978-3-642-23397-5_36</a>}, booktitle={Proc. European Conf. on Parallel Processing (Euro-Par)}, publisher={Springer}, author={Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}, year={2011}, collection={Lecture Notes in Computer Science (LNCS)} }","apa":"Graf, T., Lorenz, U., Platzner, M., &#38; Schaefers, L. (2011). Parallel Monte-Carlo Tree Search for HPC Systems. In <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i> (Vol. 6853). Berlin / Heidelberg: Springer. <a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">https://doi.org/10.1007/978-3-642-23397-5_36</a>"},"date_updated":"2022-01-06T06:55:23Z","publisher":"Springer","volume":6853,"author":[{"first_name":"Tobias","full_name":"Graf, Tobias","last_name":"Graf"},{"last_name":"Lorenz","full_name":"Lorenz, Ulf","first_name":"Ulf"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"first_name":"Lars","last_name":"Schaefers","full_name":"Schaefers, Lars"}],"date_created":"2018-04-03T15:14:56Z","title":"Parallel Monte-Carlo Tree Search for HPC Systems","doi":"10.1007/978-3-642-23397-5_36"},{"abstract":[{"text":"Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach.","lang":"eng"}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_name":"666-drzevitzky11_recosoc.pdf","file_id":"1214","access_level":"closed","file_size":666039,"creator":"florida","date_created":"2018-03-14T13:40:48Z","date_updated":"2018-03-14T13:40:48Z"}],"status":"public","type":"conference","publication":"Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-14T13:40:48Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"_id":"666","user_id":"477","department":[{"_id":"78"}],"year":"2011","citation":{"ieee":"S. Drzevitzky and M. Platzner, “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach,” in <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2011, pp. 58–65.","chicago":"Drzevitzky, Stephanie, and Marco Platzner. “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach.” In <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 58–65, 2011. <a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">https://doi.org/10.1109/ReCoSoC.2011.5981499</a>.","ama":"Drzevitzky S, Platzner M. Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach. In: <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2011:58-65. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">10.1109/ReCoSoC.2011.5981499</a>","bibtex":"@inproceedings{Drzevitzky_Platzner_2011, title={Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">10.1109/ReCoSoC.2011.5981499</a>}, booktitle={Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Drzevitzky, Stephanie and Platzner, Marco}, year={2011}, pages={58–65} }","short":"S. Drzevitzky, M. Platzner, in: Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011, pp. 58–65.","mla":"Drzevitzky, Stephanie, and Marco Platzner. “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach.” <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 2011, pp. 58–65, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">10.1109/ReCoSoC.2011.5981499</a>.","apa":"Drzevitzky, S., &#38; Platzner, M. (2011). Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach. 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