[{"ddc":["040"],"user_id":"15278","page":"559-565","_id":"567","publisher":"IEEE","has_accepted_license":"1","status":"public","quality_controlled":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"file_date_updated":"2018-03-15T10:20:24Z","citation":{"bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>"},"doi":"10.1109/HPCSim.2012.6266973","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:54Z","title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","year":"2012","author":[{"full_name":"Barrio, Pablo","first_name":"Pablo","last_name":"Barrio"},{"last_name":"Carreras","first_name":"Carlos","full_name":"Carreras, Carlos"},{"full_name":"Sierra, Roberto","first_name":"Roberto","last_name":"Sierra"},{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"}],"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"creator":"florida","date_created":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","file_size":288508,"access_level":"closed","relation":"main_file","date_updated":"2018-03-15T10:20:24Z","file_id":"1275","content_type":"application/pdf","success":1}],"date_created":"2017-10-17T12:42:42Z","abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)"},{"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","year":"2012","author":[{"full_name":"Rüthing, Christoph","first_name":"Christoph","last_name":"Rüthing"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"}],"date_updated":"2023-09-26T13:42:03Z","language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"file":[{"creator":"florida","date_created":"2018-03-15T06:49:03Z","file_name":"612-ruething_fpl12.pdf","access_level":"closed","file_size":202923,"relation":"main_file","date_updated":"2018-03-15T06:49:03Z","file_id":"1247","success":1,"content_type":"application/pdf"}],"date_created":"2017-10-17T12:42:51Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","has_accepted_license":"1","page":"559-562","publisher":"IEEE","_id":"612","user_id":"15278","ddc":["040"],"file_date_updated":"2018-03-15T06:49:03Z","citation":{"mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562."},"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}]},{"quality_controlled":"1","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","citation":{"mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>. ; 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012."},"keyword":["funding-enhance"],"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-03T09:18:33Z","date_updated":"2023-09-26T13:40:17Z","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","status":"public","year":"2012","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"id":"3118","first_name":"Tobias","last_name":"Wiersema","full_name":"Wiersema, Tobias"},{"id":"16153","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"user_id":"15278","_id":"2180","language":[{"iso":"eng"}]},{"doi":"10.1155/2012/418315","user_id":"15278","_id":"2177","language":[{"iso":"eng"}],"publisher":"Hindawi Publishing Corp.","date_updated":"2023-09-26T13:39:48Z","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","year":"2012","status":"public","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian"}],"type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-03T09:13:22Z","quality_controlled":"1","publication":"Int. Journal of Reconfigurable Computing (IJRC)","citation":{"bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>.","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012).","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int Journal of Reconfigurable Computing (IJRC)</i>. Published online 2012. doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012, doi: <a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>.","apa":"Grad, M., &#38; Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int. 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(2011). Estimation and Partitioning for CPU-Accelerator Architectures. In <i>Intel European Research and Innovation Conference</i>.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in <i>Intel European Research and Innovation Conference</i>, 2011.","short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In <i>Intel European Research and Innovation Conference</i>, 2011.","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” <i>Intel European Research and Innovation Conference</i>, 2011.","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: <i>Intel European Research and Innovation Conference</i>. ; 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }"}},{"date_created":"2018-04-03T15:11:16Z","place":"Hershey, PA, USA","type":"book_chapter","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility","citation":{"mla":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>.","bibtex":"@inbook{Plessl_Platzner_2011, place={Hershey, PA, USA}, title={Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}, DOI={<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>}, booktitle={Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}, publisher={IGI Global}, author={Plessl, Christian and Platzner, Marco}, editor={Khalgui, Mohamed and Hanisch, Hans-MichaelEditors}, year={2011} }","ama":"Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global; 2011. doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>","ieee":"C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.","apa":"Plessl, C., &#38; Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui &#38; H.-M. Hanisch (Eds.), <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>","chicago":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” In <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch. Hershey, PA, USA: IGI Global, 2011. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>.","short":"C. Plessl, M. Platzner, in: M. Khalgui, H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI Global, Hershey, PA, USA, 2011."},"project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"_id":"2202","publisher":"IGI Global","user_id":"24135","doi":"10.4018/978-1-60960-086-0","editor":[{"full_name":"Khalgui, Mohamed","first_name":"Mohamed","last_name":"Khalgui"},{"first_name":"Hans-Michael","last_name":"Hanisch","full_name":"Hanisch, Hans-Michael"}],"title":"Hardware Virtualization on Dynamically Reconfigurable Embedded Processors","year":"2011","status":"public","publication_identifier":{"isbn":["978-1-60960-086-0"]},"author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-01-06T06:55:22Z"},{"volume":6853,"doi":"10.1007/978-3-642-23397-5_36","user_id":"24135","publisher":"Springer","_id":"2204","series_title":"Lecture Notes in Computer Science (LNCS)","intvolume":"      6853","date_updated":"2022-01-06T06:55:23Z","author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"},{"first_name":"Ulf","last_name":"Lorenz","full_name":"Lorenz, Ulf"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"full_name":"Schaefers, Lars","last_name":"Schaefers","first_name":"Lars"}],"year":"2011","title":"Parallel Monte-Carlo Tree Search for HPC Systems","status":"public","department":[{"_id":"27"},{"_id":"78"}],"type":"conference","place":"Berlin / Heidelberg","date_created":"2018-04-03T15:14:56Z","citation":{"mla":"Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.” <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i>, vol. 6853, Springer, 2011, doi:<a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">10.1007/978-3-642-23397-5_36</a>.","bibtex":"@inproceedings{Graf_Lorenz_Platzner_Schaefers_2011, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={Parallel Monte-Carlo Tree Search for HPC Systems}, volume={6853}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">10.1007/978-3-642-23397-5_36</a>}, booktitle={Proc. European Conf. on Parallel Processing (Euro-Par)}, publisher={Springer}, author={Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}, year={2011}, collection={Lecture Notes in Computer Science (LNCS)} }","ama":"Graf T, Lorenz U, Platzner M, Schaefers L. Parallel Monte-Carlo Tree Search for HPC Systems. In: <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i>. Vol 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2011. doi:<a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">10.1007/978-3-642-23397-5_36</a>","ieee":"T. Graf, U. Lorenz, M. Platzner, and L. Schaefers, “Parallel Monte-Carlo Tree Search for HPC Systems,” in <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i>, 2011, vol. 6853.","apa":"Graf, T., Lorenz, U., Platzner, M., &#38; Schaefers, L. (2011). Parallel Monte-Carlo Tree Search for HPC Systems. In <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i> (Vol. 6853). Berlin / Heidelberg: Springer. <a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">https://doi.org/10.1007/978-3-642-23397-5_36</a>","chicago":"Graf, Tobias, Ulf Lorenz, Marco Platzner, and Lars Schaefers. “Parallel Monte-Carlo Tree Search for HPC Systems.” In <i>Proc. European Conf. on Parallel Processing (Euro-Par)</i>, Vol. 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer, 2011. <a href=\"https://doi.org/10.1007/978-3-642-23397-5_36\">https://doi.org/10.1007/978-3-642-23397-5_36</a>.","short":"T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, Berlin / Heidelberg, 2011."},"publication":"Proc. European Conf. on Parallel Processing (Euro-Par)"},{"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"}],"file_date_updated":"2018-03-14T13:40:48Z","citation":{"apa":"Drzevitzky, S., &#38; Platzner, M. (2011). Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach. In <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i> (pp. 58–65). <a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">https://doi.org/10.1109/ReCoSoC.2011.5981499</a>","ieee":"S. Drzevitzky and M. Platzner, “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach,” in <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2011, pp. 58–65.","chicago":"Drzevitzky, Stephanie, and Marco Platzner. “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach.” In <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 58–65, 2011. <a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">https://doi.org/10.1109/ReCoSoC.2011.5981499</a>.","short":"S. Drzevitzky, M. Platzner, in: Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011, pp. 58–65.","mla":"Drzevitzky, Stephanie, and Marco Platzner. “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach.” <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 2011, pp. 58–65, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">10.1109/ReCoSoC.2011.5981499</a>.","ama":"Drzevitzky S, Platzner M. Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach. In: <i>Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2011:58-65. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">10.1109/ReCoSoC.2011.5981499</a>","bibtex":"@inproceedings{Drzevitzky_Platzner_2011, title={Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2011.5981499\">10.1109/ReCoSoC.2011.5981499</a>}, booktitle={Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Drzevitzky, Stephanie and Platzner, Marco}, year={2011}, pages={58–65} }"},"has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"477","page":"58-65","_id":"666","abstract":[{"lang":"eng","text":"Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach."}],"publication":"Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","type":"conference","department":[{"_id":"78"}],"file":[{"creator":"florida","date_created":"2018-03-14T13:40:48Z","relation":"main_file","date_updated":"2018-03-14T13:40:48Z","file_name":"666-drzevitzky11_recosoc.pdf","access_level":"closed","file_size":666039,"file_id":"1214","success":1,"content_type":"application/pdf"}],"date_created":"2017-10-17T12:43:01Z","date_updated":"2022-01-06T07:03:14Z","title":"Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach","year":"2011","author":[{"full_name":"Drzevitzky, Stephanie","last_name":"Drzevitzky","first_name":"Stephanie"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"doi":"10.1109/ReCoSoC.2011.5981499","language":[{"iso":"eng"}]},{"department":[{"_id":"78"}],"type":"conference","date_created":"2019-07-10T11:03:22Z","citation":{"short":"A. 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MyoElectric Controls Symposium (MEC)</i>. ; 2011."},"language":[{"iso":"eng"}],"_id":"10638","user_id":"3118","title":"Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems","status":"public","year":"2011","author":[{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"full_name":"Robrecht, Michael","last_name":"Robrecht","first_name":"Michael"},{"first_name":"Martin","last_name":"Hahn","full_name":"Hahn, Martin"},{"full_name":"Winkler, Michael","last_name":"Winkler","first_name":"Michael"}],"date_updated":"2022-01-06T06:50:49Z"},{"_id":"10678","publisher":"Paderborn University","language":[{"iso":"eng"}],"user_id":"3118","author":[{"first_name":"Nikolaos","last_name":"Ikonomakis","full_name":"Ikonomakis, Nikolaos"}],"title":"PinSim: Schnelle Simulation mit Pintools","year":"2011","status":"public","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:23:19Z","department":[{"_id":"78"}],"type":"bachelorsthesis","citation":{"ama":"Ikonomakis N. <i>PinSim: Schnelle Simulation Mit Pintools</i>. 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IEEE. <a href=\"https://doi.org/10.1109/fpl.2011.42\">https://doi.org/10.1109/fpl.2011.42</a>","bibtex":"@inproceedings{Agne_Platzner_Lübbers_2011, title={Memory Virtualization for Multithreaded Reconfigurable Hardware}, DOI={<a href=\"https://doi.org/10.1109/fpl.2011.42\">10.1109/fpl.2011.42</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Agne, Andreas and Platzner, Marco and Lübbers, Enno}, year={2011}, pages={185–188} }","ama":"Agne A, Platzner M, Lübbers E. Memory Virtualization for Multithreaded Reconfigurable Hardware. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. 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Design and architectures for dependable embedded systems. In: <i>Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11</i>. ; 2011. doi:<a href=\"https://doi.org/10.1145/2039370.2039384\">10.1145/2039370.2039384</a>","bibtex":"@inproceedings{Henkel_Hedrich_Herkersdorf_Kapitza_Lohmann_Marwedel_Platzner_Rosenstiel_Schlichtmann_Spinczyk_et al._2011, title={Design and architectures for dependable embedded systems}, DOI={<a href=\"https://doi.org/10.1145/2039370.2039384\">10.1145/2039370.2039384</a>}, booktitle={Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11}, author={Henkel, Jörg and Hedrich, Lars and Herkersdorf, Andreas and Kapitza, Rüdiger and Lohmann, Daniel and Marwedel, Peter and Platzner, Marco and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Spinczyk, Olaf and et al.}, year={2011} }","mla":"Henkel, Jörg, et al. “Design and Architectures for Dependable Embedded Systems.” <i>Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11</i>, 2011, doi:<a href=\"https://doi.org/10.1145/2039370.2039384\">10.1145/2039370.2039384</a>.","chicago":"Henkel, Jörg, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, et al. “Design and Architectures for Dependable Embedded Systems.” In <i>Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11</i>, 2011. <a href=\"https://doi.org/10.1145/2039370.2039384\">https://doi.org/10.1145/2039370.2039384</a>.","short":"J. Henkel, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, L. Bauer, J. Teich, N. Wehn, H.-J. Wunderlich, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, in: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011.","apa":"Henkel, J., Hedrich, L., Herkersdorf, A., Kapitza, R., Lohmann, D., Marwedel, P., … Härtig, H. (2011). Design and architectures for dependable embedded systems. In <i>Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11</i>. <a href=\"https://doi.org/10.1145/2039370.2039384\">https://doi.org/10.1145/2039370.2039384</a>","ieee":"J. Henkel <i>et al.</i>, “Design and architectures for dependable embedded systems,” in <i>Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11</i>, 2011."},"publication":"Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11","date_created":"2019-10-04T22:44:36Z","department":[{"_id":"78"}],"type":"conference"},{"date_updated":"2023-09-26T13:44:11Z","title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","year":"2011","status":"public","author":[{"last_name":"Meyer","first_name":"Björn","full_name":"Meyer, Björn"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"},{"orcid":"0000-0001-7059-9862","first_name":"Jens","last_name":"Förstner","full_name":"Förstner, Jens","id":"158"}],"doi":"10.1109/SAAHPC.2011.12","user_id":"15278","page":"60-63","language":[{"iso":"eng"}],"_id":"2194","publisher":"IEEE Computer Society","quality_controlled":"1","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30","grant_number":"01|H11004A"}],"publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","citation":{"apa":"Meyer, B., Plessl, C., &#38; Förstner, J. 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IEEE Computer Society; 2011:60-63. doi:<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>","bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }"},"type":"conference","keyword":["tet_topic_hpc"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"date_created":"2018-04-03T14:55:57Z"}]