[{"date_updated":"2024-05-15T13:29:49Z","year":"2023","status":"public","title":"Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen","author":[{"last_name":"Hamm","first_name":"Robin","full_name":"Hamm, Robin"}],"user_id":"398","_id":"54246","language":[{"iso":"ger"}],"publisher":"Paderborn University","citation":{"bibtex":"@book{Hamm_2023, title={Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen}, publisher={Paderborn University}, author={Hamm, Robin}, year={2023} }","ama":"Hamm R. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University; 2023.","mla":"Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University, 2023.","short":"R. Hamm, Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen, Paderborn University, 2023.","chicago":"Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University, 2023.","ieee":"R. Hamm, <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University, 2023.","apa":"Hamm, R. (2023). <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University."},"supervisor":[{"first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","id":"74287"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"type":"bachelorsthesis","department":[{"_id":"78"}],"date_created":"2024-05-13T14:01:01Z"},{"_id":"52480","publisher":"Paderborn University","language":[{"iso":"eng"}],"user_id":"398","author":[{"first_name":"Alexander","last_name":"Klassen","full_name":"Klassen, Alexander"}],"title":"Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices","year":"2023","status":"public","date_updated":"2024-05-15T13:28:54Z","date_created":"2024-03-11T16:06:00Z","department":[{"_id":"78"}],"type":"bachelorsthesis","supervisor":[{"id":"74287","first_name":"Lennart","orcid":"0000-0003-3789-6034","last_name":"Clausing","full_name":"Clausing, Lennart"}],"citation":{"ama":"Klassen A. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University; 2023.","bibtex":"@book{Klassen_2023, title={Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices}, publisher={Paderborn University}, author={Klassen, Alexander}, year={2023} }","mla":"Klassen, Alexander. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University, 2023.","short":"A. Klassen, Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices, Paderborn University, 2023.","chicago":"Klassen, Alexander. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University, 2023.","apa":"Klassen, A. (2023). <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University.","ieee":"A. Klassen, <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University, 2023."}},{"date_updated":"2024-05-15T13:24:38Z","author":[{"full_name":"Tsague Dingo, Jorian","last_name":"Tsague Dingo","first_name":"Jorian"}],"year":"2023","status":"public","title":"Ein Simulator für Schedulability-Experimente mit periodischen Tasks auf FPGAs","user_id":"398","publisher":"Paderborn University","_id":"54298","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"citation":{"mla":"Tsague Dingo, Jorian. <i>Ein Simulator Für Schedulability-Experimente Mit Periodischen Tasks Auf FPGAs</i>. Paderborn University, 2023.","bibtex":"@book{Tsague Dingo_2023, title={Ein Simulator für Schedulability-Experimente mit periodischen Tasks auf FPGAs}, publisher={Paderborn University}, author={Tsague Dingo, Jorian}, year={2023} }","ama":"Tsague Dingo J. <i>Ein Simulator Für Schedulability-Experimente Mit Periodischen Tasks Auf FPGAs</i>. Paderborn University; 2023.","ieee":"J. Tsague Dingo, <i>Ein Simulator für Schedulability-Experimente mit periodischen Tasks auf FPGAs</i>. Paderborn University, 2023.","apa":"Tsague Dingo, J. (2023). <i>Ein Simulator für Schedulability-Experimente mit periodischen Tasks auf FPGAs</i>. Paderborn University.","short":"J. Tsague Dingo, Ein Simulator Für Schedulability-Experimente Mit Periodischen Tasks Auf FPGAs, Paderborn University, 2023.","chicago":"Tsague Dingo, Jorian. <i>Ein Simulator Für Schedulability-Experimente Mit Periodischen Tasks Auf FPGAs</i>. Paderborn University, 2023."},"department":[{"_id":"78"}],"type":"bachelorsthesis","date_created":"2024-05-15T13:24:34Z"},{"user_id":"398","_id":"54299","publisher":"Paderborn University","language":[{"iso":"eng"}],"date_updated":"2024-05-15T13:26:23Z","author":[{"first_name":"Mathis","last_name":"Brede","full_name":"Brede, Mathis"}],"title":"Evaluation of Classifier Migration Between Multiple XCS Populations","year":"2023","status":"public","department":[{"_id":"78"}],"type":"mastersthesis","date_created":"2024-05-15T13:26:17Z","citation":{"apa":"Brede, M. (2023). <i>Evaluation of Classifier Migration Between Multiple XCS Populations</i>. Paderborn University.","ieee":"M. Brede, <i>Evaluation of Classifier Migration Between Multiple XCS Populations</i>. Paderborn University, 2023.","chicago":"Brede, Mathis. <i>Evaluation of Classifier Migration Between Multiple XCS Populations</i>. Paderborn University, 2023.","short":"M. Brede, Evaluation of Classifier Migration Between Multiple XCS Populations, Paderborn University, 2023.","mla":"Brede, Mathis. <i>Evaluation of Classifier Migration Between Multiple XCS Populations</i>. Paderborn University, 2023.","ama":"Brede M. <i>Evaluation of Classifier Migration Between Multiple XCS Populations</i>. Paderborn University; 2023.","bibtex":"@book{Brede_2023, title={Evaluation of Classifier Migration Between Multiple XCS Populations}, publisher={Paderborn University}, author={Brede, Mathis}, year={2023} }"},"supervisor":[{"first_name":"Tim ","last_name":"Hansmeier","full_name":"Hansmeier, Tim "}]},{"date_updated":"2024-05-15T13:27:26Z","status":"public","title":"Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor","year":"2023","author":[{"first_name":"Alexander","last_name":"Nowosad","full_name":"Nowosad, Alexander"}],"user_id":"398","_id":"54300","language":[{"iso":"eng"}],"publisher":"Paderborn University","citation":{"short":"A. Nowosad, Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor, Paderborn University, 2023.","chicago":"Nowosad, Alexander. <i>Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor</i>. Paderborn University, 2023.","ieee":"A. Nowosad, <i>Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor</i>. Paderborn University, 2023.","apa":"Nowosad, A. (2023). <i>Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor</i>. Paderborn University.","bibtex":"@book{Nowosad_2023, title={Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor}, publisher={Paderborn University}, author={Nowosad, Alexander}, year={2023} }","ama":"Nowosad A. <i>Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor</i>. Paderborn University; 2023.","mla":"Nowosad, Alexander. <i>Design and Realization of an Intra-FPGA ROS 2 Communication Infrastructure for the ReconROS Executor</i>. Paderborn University, 2023."},"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2024-05-15T13:27:19Z"},{"citation":{"mla":"Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University, 2023.","bibtex":"@book{Evers_2023, title={Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation}, publisher={Paderborn University}, author={Evers, Gerrit}, year={2023} }","ama":"Evers G. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University; 2023.","ieee":"G. Evers, <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University, 2023.","apa":"Evers, G. (2023). <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University.","chicago":"Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University, 2023.","short":"G. Evers, Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation, Paderborn University, 2023."},"supervisor":[{"id":"74287","full_name":"Clausing, Lennart","first_name":"Lennart","orcid":"0000-0003-3789-6034","last_name":"Clausing"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2024-05-13T13:59:09Z","department":[{"_id":"78"}],"type":"bachelorsthesis","author":[{"full_name":"Evers, Gerrit","last_name":"Evers","first_name":"Gerrit"}],"year":"2023","title":"Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation","status":"public","date_updated":"2024-05-15T13:31:08Z","language":[{"iso":"ger"}],"_id":"54242","publisher":"Paderborn University","user_id":"398"},{"user_id":"398","_id":"46075","language":[{"iso":"eng"}],"publisher":"Paderborn University","date_updated":"2024-05-15T13:32:14Z","author":[{"last_name":"Raeisi Nafchi","first_name":"Masood","full_name":"Raeisi Nafchi, Masood"}],"year":"2023","status":"public","title":"Reconfigurable Random Forest Implementation on FPGA","department":[{"_id":"78"}],"type":"mastersthesis","date_created":"2023-07-18T08:55:14Z","supervisor":[{"id":"74287","orcid":"0000-0003-3789-6034","last_name":"Clausing","first_name":"Lennart","full_name":"Clausing, Lennart"}],"citation":{"ama":"Raeisi Nafchi M. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University; 2023.","bibtex":"@book{Raeisi Nafchi_2023, title={Reconfigurable Random Forest Implementation on FPGA}, publisher={Paderborn University}, author={Raeisi Nafchi, Masood}, year={2023} }","mla":"Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023.","short":"M. Raeisi Nafchi, Reconfigurable Random Forest Implementation on FPGA, Paderborn University, 2023.","chicago":"Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023.","apa":"Raeisi Nafchi, M. (2023). <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University.","ieee":"M. Raeisi Nafchi, <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023."}},{"status":"public","has_accepted_license":"1","publisher":"Heinz Nixdorf Institut, Universität Paderborn","_id":"45863","page":"247","volume":412,"ddc":["000"],"user_id":"1112","citation":{"bibtex":"@book{Haake_Meyer auf der Heide_Platzner_Wachsmuth_Wehrheim_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, volume={412}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1797\">10.17619/UNIPB/1-1797</a>}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }","ama":"Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H. <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>. Vol 412. Heinz Nixdorf Institut, Universität Paderborn; 2023. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1797\">10.17619/UNIPB/1-1797</a>","short":"C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim, On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023.","chicago":"Haake, Claus-Jochen, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim. <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>. Vol. 412. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. <a href=\"https://doi.org/10.17619/UNIPB/1-1797\">https://doi.org/10.17619/UNIPB/1-1797</a>.","ieee":"C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i>, vol. 412. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023.","apa":"Haake, C.-J., Meyer auf der Heide, F., Platzner, M., Wachsmuth, H., &#38; Wehrheim, H. (2023). <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i> (Vol. 412). Heinz Nixdorf Institut, Universität Paderborn. <a href=\"https://doi.org/10.17619/UNIPB/1-1797\">https://doi.org/10.17619/UNIPB/1-1797</a>","mla":"Haake, Claus-Jochen, et al. <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>. Heinz Nixdorf Institut, Universität Paderborn, 2023, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1797\">10.17619/UNIPB/1-1797</a>."},"file_date_updated":"2023-07-05T07:19:14Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "},{"_id":"2","name":"SFB 901 - A: SFB 901 - Project Area A"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901 - A1: SFB 901 - Möglichkeiten und Grenzen lokaler Strategien in dynamischen Netzen (Subproject A1)","grant_number":"160364472","_id":"5"},{"_id":"7","grant_number":"160364472","name":"SFB 901 - A3: SFB 901 - Der Markt für Services: Anreize, Algorithmen, Implementation (Subproject A3)"},{"_id":"8","grant_number":"160364472","name":"SFB 901 - A4: SFB 901 - Empirische Analysen in Märkten für OTF Dienstleistungen (Subproject A4)"},{"_id":"9","grant_number":"160364472","name":"SFB 901 - B1: SFB 901 - Parametrisierte Servicespezifikation (Subproject B1)"},{"name":"SFB 901 - B2: Konfiguration und Bewertung (B02)","_id":"10","grant_number":"160364472"},{"name":"SFB 901 - B3: SFB 901 - Subproject B3","_id":"11"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"},{"_id":"13","grant_number":"160364472","name":"SFB 901 - C1: SFB 901 - Subproject C1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen (Subproject C2)"},{"name":"SFB 901 - C4: SFB 901 - On-The-Fly Compute Centers II: Ausführung komponierter Dienste in konfigurierbaren Rechenzentren (Subproject C4)","grant_number":"160364472","_id":"16"},{"name":"SFB 901 - C5: SFB 901 - Subproject C5","_id":"17"},{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"name":"SFB 901 - T2: SFB 901 -Subproject T2","grant_number":"160364472","_id":"84"}],"place":"Paderborn","oa":"1","publication_identifier":{"unknown":["978-3-947647-31-6"]},"author":[{"id":"20801","full_name":"Haake, Claus-Jochen","first_name":"Claus-Jochen","last_name":"Haake"},{"id":"15523","full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","last_name":"Meyer auf der Heide"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"id":"3900","full_name":"Wachsmuth, Henning","first_name":"Henning","last_name":"Wachsmuth"},{"id":"573","full_name":"Wehrheim, Heike","last_name":"Wehrheim","first_name":"Heike"}],"title":"On-The-Fly Computing -- Individualized IT-services in dynamic markets","year":"2023","intvolume":"       412","date_updated":"2024-07-12T12:07:59Z","language":[{"iso":"eng"}],"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","alternative_title":["Collaborative Research Centre 901 (2011 – 2023)"],"doi":"10.17619/UNIPB/1-1797","abstract":[{"text":"In the proposal for our CRC in 2011, we formulated a vision of markets for\r\nIT services that describes an approach to the provision of such services\r\nthat was novel at that time and, to a large extent, remains so today:\r\n„Our vision of on-the-fly computing is that of IT services individually and\r\nautomatically configured and brought to execution from flexibly combinable\r\nservices traded on markets. At the same time, we aim at organizing\r\nmarkets whose participants maintain a lively market of services through\r\nappropriate entrepreneurial actions.“\r\nOver the last 12 years, we have developed methods and techniques to\r\naddress problems critical to the convenient, efficient, and secure use of\r\non-the-fly computing. Among other things, we have made the description\r\nof services more convenient by allowing natural language input,\r\nincreased the quality of configured services through (natural language)\r\ninteraction and more efficient configuration processes and analysis\r\nprocedures, made the quality of (the products of) providers in the\r\nmarketplace transparent through reputation systems, and increased the\r\nresource efficiency of execution through reconfigurable heterogeneous\r\ncomputing nodes and an integrated treatment of service description and\r\nconfiguration. We have also developed network infrastructures that have\r\na high degree of adaptivity, scalability, efficiency, and reliability, and\r\nprovide cryptographic guarantees of anonymity and security for market\r\nparticipants and their products and services.\r\nTo demonstrate the pervasiveness of the OTF computing approach, we\r\nhave implemented a proof-of-concept for OTF computing that can run\r\ntypical scenarios of an OTF market. We illustrated the approach using\r\na cutting-edge application scenario – automated machine learning (AutoML).\r\nFinally, we have been pushing our work for the perpetuation of\r\nOn-The-Fly Computing beyond the SFB and sharing the expertise gained\r\nin the SFB in events with industry partners as well as transfer projects.\r\nThis work required a broad spectrum of expertise. Computer scientists\r\nand economists with research interests such as computer networks and\r\ndistributed algorithms, security and cryptography, software engineering\r\nand verification, configuration and machine learning, computer engineering\r\nand HPC, microeconomics and game theory, business informatics\r\nand management have successfully collaborated here.","lang":"eng"}],"date_created":"2023-07-05T07:16:51Z","file":[{"creator":"ups","date_created":"2023-07-05T07:15:55Z","file_size":15480050,"access_level":"open_access","file_name":"SFB-Buch-Final.pdf","date_updated":"2023-07-05T07:19:14Z","relation":"main_file","content_type":"application/pdf","file_id":"45864"}],"department":[{"_id":"7"},{"_id":"78"},{"_id":"26"}],"type":"book"},{"file_date_updated":"2023-05-10T13:52:14Z","citation":{"apa":"Ahmed, Q. A., Awais, M., &#38; Platzner, M. (2023). MAAS: Hiding Trojans in Approximate Circuits. <i>The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA</i>. The 24th International Symposium on Quality Electronic Design (ISQED’23), San Fransico CA 94023-0607, USA.","ieee":"Q. A. Ahmed, M. Awais, and M. Platzner, “MAAS: Hiding Trojans in Approximate Circuits,” presented at the The 24th International Symposium on Quality Electronic Design (ISQED’23), San Fransico CA 94023-0607, USA, 2023.","short":"Q.A. Ahmed, M. Awais, M. Platzner, in: The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA, 2023.","chicago":"Ahmed, Qazi Arbab, Muhammad Awais, and Marco Platzner. “MAAS: Hiding Trojans in Approximate Circuits.” In <i>The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA</i>, 2023.","mla":"Ahmed, Qazi Arbab, et al. “MAAS: Hiding Trojans in Approximate Circuits.” <i>The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA</i>, 2023.","ama":"Ahmed QA, Awais M, Platzner M. MAAS: Hiding Trojans in Approximate Circuits. In: <i>The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA</i>. ; 2023.","bibtex":"@inproceedings{Ahmed_Awais_Platzner_2023, title={MAAS: Hiding Trojans in Approximate Circuits}, booktitle={The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA}, author={Ahmed, Qazi Arbab and Awais, Muhammad and Platzner, Marco}, year={2023} }"},"project":[{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"name":"SFB 901 - B4: SFB 901 - Subproject B4","_id":"12"},{"name":"SFB 901: SFB 901","_id":"1"}],"oa":"1","status":"public","conference":{"end_date":"2023-04-07","name":"The 24th International Symposium on Quality Electronic Design (ISQED'23)","start_date":"2023-04-05","location":"San Fransico CA 94023-0607, USA"},"has_accepted_license":"1","_id":"44194","ddc":["620"],"user_id":"72764","publication":"The 24th International Symposium on Quality Electronic Design (ISQED'23), San Francisco, Califorina USA","file":[{"date_created":"2023-04-26T13:03:54Z","creator":"qazi","file_id":"44196","content_type":"application/pdf","relation":"main_file","date_updated":"2023-05-10T13:52:14Z","file_name":"s4Bp4-041.pdf","file_size":614626,"access_level":"open_access"}],"date_created":"2023-04-26T13:04:56Z","type":"conference","department":[{"_id":"78"}],"year":"2023","title":"MAAS: Hiding Trojans in Approximate Circuits","author":[{"last_name":"Ahmed","first_name":"Qazi Arbab","orcid":"0000-0002-1837-2254","full_name":"Ahmed, Qazi Arbab","id":"72764"},{"full_name":"Awais, Muhammad","last_name":"Awais","first_name":"Muhammad"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"date_updated":"2023-05-10T13:52:14Z","language":[{"iso":"eng"}]},{"project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1","grant_number":"160364472"}],"citation":{"chicago":"Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023.","short":"M. Raeisi Nafchi, Reconfigurable Random Forest Implementation on FPGA, Paderborn University, 2023.","apa":"Raeisi Nafchi, M. (2023). <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University.","ieee":"M. Raeisi Nafchi, <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023.","ama":"Raeisi Nafchi M. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University; 2023.","bibtex":"@book{Raeisi Nafchi_2023, title={Reconfigurable Random Forest Implementation on FPGA}, publisher={Paderborn University}, author={Raeisi Nafchi, Masood}, year={2023} }","mla":"Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023."},"supervisor":[{"first_name":"Marco ","last_name":"Platzner","full_name":"Platzner, Marco "}],"department":[{"_id":"78"}],"type":"mastersthesis","date_created":"2023-07-09T13:01:10Z","date_updated":"2023-07-09T13:07:25Z","author":[{"last_name":"Raeisi Nafchi","first_name":"Masood","full_name":"Raeisi Nafchi, Masood"}],"year":"2023","title":"Reconfigurable Random Forest Implementation on FPGA","status":"public","user_id":"398","language":[{"iso":"eng"}],"_id":"45917","publisher":"Paderborn University"},{"date_updated":"2023-07-09T13:06:37Z","year":"2023","status":"public","title":"Data Analytics for Predictive Maintenance of Time Series Data","author":[{"first_name":"Nihal","last_name":"Yadalam Murali Kumar","full_name":"Yadalam Murali Kumar, Nihal"}],"user_id":"398","_id":"45916","publisher":"Paderborn University","language":[{"iso":"eng"}],"project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1","grant_number":"160364472"}],"citation":{"apa":"Yadalam Murali Kumar, N. (2023). <i>Data Analytics for Predictive Maintenance of Time Series Data</i>. Paderborn University.","ieee":"N. Yadalam Murali Kumar, <i>Data Analytics for Predictive Maintenance of Time Series Data</i>. Paderborn University, 2023.","short":"N. Yadalam Murali Kumar, Data Analytics for Predictive Maintenance of Time Series Data, Paderborn University, 2023.","chicago":"Yadalam Murali Kumar, Nihal. <i>Data Analytics for Predictive Maintenance of Time Series Data</i>. Paderborn University, 2023.","mla":"Yadalam Murali Kumar, Nihal. <i>Data Analytics for Predictive Maintenance of Time Series Data</i>. Paderborn University, 2023.","ama":"Yadalam Murali Kumar N. <i>Data Analytics for Predictive Maintenance of Time Series Data</i>. Paderborn University; 2023.","bibtex":"@book{Yadalam Murali Kumar_2023, title={Data Analytics for Predictive Maintenance of Time Series Data}, publisher={Paderborn University}, author={Yadalam Murali Kumar, Nihal}, year={2023} }"},"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2023-07-09T12:59:28Z"},{"citation":{"mla":"Ahmed, Qazi Arbab, et al. “MAAS: Hiding Trojans in Approximate Circuits.” <i>2023 24th International Symposium on Quality Electronic Design (ISQED)</i>, IEEE, 2023, doi:<a href=\"https://doi.org/10.1109/isqed57927.2023.10129286\">10.1109/isqed57927.2023.10129286</a>.","ama":"Ahmed QA, Awais M, Platzner M. MAAS: Hiding Trojans in Approximate Circuits. In: <i>2023 24th International Symposium on Quality Electronic Design (ISQED)</i>. IEEE; 2023. doi:<a href=\"https://doi.org/10.1109/isqed57927.2023.10129286\">10.1109/isqed57927.2023.10129286</a>","bibtex":"@inproceedings{Ahmed_Awais_Platzner_2023, title={MAAS: Hiding Trojans in Approximate Circuits}, DOI={<a href=\"https://doi.org/10.1109/isqed57927.2023.10129286\">10.1109/isqed57927.2023.10129286</a>}, booktitle={2023 24th International Symposium on Quality Electronic Design (ISQED)}, publisher={IEEE}, author={Ahmed, Qazi Arbab and Awais, Muhammad and Platzner, Marco}, year={2023} }","apa":"Ahmed, Q. A., Awais, M., &#38; Platzner, M. (2023). MAAS: Hiding Trojans in Approximate Circuits. <i>2023 24th International Symposium on Quality Electronic Design (ISQED)</i>. <a href=\"https://doi.org/10.1109/isqed57927.2023.10129286\">https://doi.org/10.1109/isqed57927.2023.10129286</a>","ieee":"Q. A. Ahmed, M. Awais, and M. Platzner, “MAAS: Hiding Trojans in Approximate Circuits,” 2023, doi: <a href=\"https://doi.org/10.1109/isqed57927.2023.10129286\">10.1109/isqed57927.2023.10129286</a>.","short":"Q.A. Ahmed, M. Awais, M. Platzner, in: 2023 24th International Symposium on Quality Electronic Design (ISQED), IEEE, 2023.","chicago":"Ahmed, Qazi Arbab, Muhammad Awais, and Marco Platzner. “MAAS: Hiding Trojans in Approximate Circuits.” In <i>2023 24th International Symposium on Quality Electronic Design (ISQED)</i>. IEEE, 2023. <a href=\"https://doi.org/10.1109/isqed57927.2023.10129286\">https://doi.org/10.1109/isqed57927.2023.10129286</a>."},"publication":"2023 24th International Symposium on Quality Electronic Design (ISQED)","date_created":"2026-02-11T10:19:40Z","department":[{"_id":"78"}],"type":"conference","author":[{"full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed","first_name":"Qazi Arbab"},{"first_name":"Muhammad","last_name":"Awais","full_name":"Awais, Muhammad"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"status":"public","title":"MAAS: Hiding Trojans in Approximate Circuits","year":"2023","publication_status":"published","date_updated":"2026-02-11T10:20:32Z","publisher":"IEEE","_id":"64114","user_id":"64665","doi":"10.1109/isqed57927.2023.10129286"},{"_id":"54244","publisher":"Paderborn University","language":[{"iso":"eng"}],"user_id":"55631","title":"Design and Implementation of a RadioML Demonstrator based on an RFSoC Platform","status":"public","year":"2023","author":[{"first_name":"Salem","last_name":"AlAidroos","full_name":"AlAidroos, Salem"}],"date_updated":"2026-04-27T14:20:33Z","date_created":"2024-05-13T13:59:16Z","type":"mastersthesis","department":[{"_id":"78"}],"citation":{"bibtex":"@book{AlAidroos_2023, title={Design and Implementation of a RadioML Demonstrator based on an RFSoC Platform}, publisher={Paderborn University}, author={AlAidroos, Salem}, year={2023} }","ama":"AlAidroos S. <i>Design and Implementation of a RadioML Demonstrator Based on an RFSoC Platform</i>. Paderborn University; 2023.","mla":"AlAidroos, Salem. <i>Design and Implementation of a RadioML Demonstrator Based on an RFSoC Platform</i>. Paderborn University, 2023.","short":"S. AlAidroos, Design and Implementation of a RadioML Demonstrator Based on an RFSoC Platform, Paderborn University, 2023.","chicago":"AlAidroos, Salem. <i>Design and Implementation of a RadioML Demonstrator Based on an RFSoC Platform</i>. Paderborn University, 2023.","ieee":"S. AlAidroos, <i>Design and Implementation of a RadioML Demonstrator based on an RFSoC Platform</i>. Paderborn University, 2023.","apa":"AlAidroos, S. (2023). <i>Design and Implementation of a RadioML Demonstrator based on an RFSoC Platform</i>. Paderborn University."},"supervisor":[{"orcid":"0000-0003-4987-5708","last_name":"Jentzsch","first_name":"Felix","full_name":"Jentzsch, Felix","id":"55631"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}]},{"user_id":"55631","publisher":"Paderborn University","_id":"54243","language":[{"iso":"eng"}],"date_updated":"2026-04-27T14:20:58Z","status":"public","year":"2023","title":"Demonstrator for Dataflow-based DNN Acceleration for Vision Applications on Platform FPGAs","author":[{"first_name":"Marvin Osaretin","last_name":"Oviasogie","full_name":"Oviasogie, Marvin Osaretin"}],"type":"bachelorsthesis","department":[{"_id":"78"}],"date_created":"2024-05-13T13:58:31Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"supervisor":[{"orcid":"0000-0003-4987-5708","first_name":"Felix","last_name":"Jentzsch","full_name":"Jentzsch, Felix","id":"55631"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"citation":{"short":"M.O. Oviasogie, Demonstrator for Dataflow-Based DNN Acceleration for Vision Applications on Platform FPGAs, Paderborn University, 2023.","chicago":"Oviasogie, Marvin Osaretin. <i>Demonstrator for Dataflow-Based DNN Acceleration for Vision Applications on Platform FPGAs</i>. Paderborn University, 2023.","ieee":"M. O. Oviasogie, <i>Demonstrator for Dataflow-based DNN Acceleration for Vision Applications on Platform FPGAs</i>. Paderborn University, 2023.","apa":"Oviasogie, M. O. (2023). <i>Demonstrator for Dataflow-based DNN Acceleration for Vision Applications on Platform FPGAs</i>. Paderborn University.","bibtex":"@book{Oviasogie_2023, title={Demonstrator for Dataflow-based DNN Acceleration for Vision Applications on Platform FPGAs}, publisher={Paderborn University}, author={Oviasogie, Marvin Osaretin}, year={2023} }","ama":"Oviasogie MO. <i>Demonstrator for Dataflow-Based DNN Acceleration for Vision Applications on Platform FPGAs</i>. Paderborn University; 2023.","mla":"Oviasogie, Marvin Osaretin. <i>Demonstrator for Dataflow-Based DNN Acceleration for Vision Applications on Platform FPGAs</i>. Paderborn University, 2023."}},{"year":"2023","title":"Development of a Power Analysis Framework for Embedded FPGA Accelerators","status":"public","author":[{"full_name":"Reuter, Lucas David","first_name":"Lucas David","last_name":"Reuter"}],"date_updated":"2026-04-27T14:21:10Z","publisher":"Paderborn University","_id":"54241","language":[{"iso":"eng"}],"user_id":"55631","citation":{"mla":"Reuter, Lucas David. <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University, 2023.","bibtex":"@book{Reuter_2023, title={Development of a Power Analysis Framework for Embedded FPGA Accelerators}, publisher={Paderborn University}, author={Reuter, Lucas David}, year={2023} }","ama":"Reuter LD. <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University; 2023.","ieee":"L. D. Reuter, <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University, 2023.","apa":"Reuter, L. D. (2023). <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University.","short":"L.D. Reuter, Development of a Power Analysis Framework for Embedded FPGA Accelerators, Paderborn University, 2023.","chicago":"Reuter, Lucas David. <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University, 2023."},"supervisor":[{"id":"55631","full_name":"Jentzsch, Felix","first_name":"Felix","last_name":"Jentzsch","orcid":"0000-0003-4987-5708"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2024-05-13T13:56:45Z","type":"bachelorsthesis","department":[{"_id":"78"}]},{"project":[{"name":"SFB 901: SFB 901","_id":"1"},{"name":"SFB 901 - B: SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901 - B4: SFB 901 - Subproject B4","_id":"12"}],"citation":{"mla":"Witschen, Linus Matthias, et al. “Search Space Characterization for Approximate Logic Synthesis .” <i>2022 59th ACM/IEEE Design Automation Conference (DAC)</i>.","bibtex":"@inproceedings{Witschen_Wiersema_Reuter_Platzner, title={Search Space Characterization for Approximate Logic Synthesis }, booktitle={2022 59th ACM/IEEE Design Automation Conference (DAC)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Reuter, Lucas David and Platzner, Marco} }","ama":"Witschen LM, Wiersema T, Reuter LD, Platzner M. Search Space Characterization for Approximate Logic Synthesis . In: <i>2022 59th ACM/IEEE Design Automation Conference (DAC)</i>.","ieee":"L. M. Witschen, T. Wiersema, L. D. Reuter, and M. Platzner, “Search Space Characterization for Approximate Logic Synthesis ,” presented at the 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.","apa":"Witschen, L. M., Wiersema, T., Reuter, L. D., &#38; Platzner, M. (n.d.). Search Space Characterization for Approximate Logic Synthesis . <i>2022 59th ACM/IEEE Design Automation Conference (DAC)</i>. 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.","short":"L.M. Witschen, T. Wiersema, L.D. Reuter, M. Platzner, in: 2022 59th ACM/IEEE Design Automation Conference (DAC), n.d.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Lucas David Reuter, and Marco Platzner. “Search Space Characterization for Approximate Logic Synthesis .” In <i>2022 59th ACM/IEEE Design Automation Conference (DAC)</i>, n.d."},"publication":"2022 59th ACM/IEEE Design Automation Conference (DAC)","department":[{"_id":"78"}],"type":"conference","date_created":"2022-02-22T07:51:38Z","publication_status":"accepted","date_updated":"2022-02-22T07:51:42Z","author":[{"id":"49051","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","last_name":"Witschen"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema","id":"3118"},{"full_name":"Reuter, Lucas David","last_name":"Reuter","first_name":"Lucas David"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"conference":{"name":"2022 59th ACM/IEEE Design Automation Conference (DAC)","start_date":"2022-07-10","location":"San Francisco, USA","end_date":"2022-07-14"},"status":"public","year":"2022","title":"Search Space Characterization for Approximate Logic Synthesis ","user_id":"49051","language":[{"iso":"eng"}],"_id":"29945"},{"language":[{"iso":"eng"}],"_id":"29865","user_id":"49051","author":[{"id":"49051","first_name":"Linus Matthias","last_name":"Witschen","full_name":"Witschen, Linus Matthias"},{"last_name":"Wiersema","first_name":"Tobias","full_name":"Wiersema, Tobias","id":"3118"},{"first_name":"Matthias","last_name":"Artmann","full_name":"Artmann, Matthias"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"conference":{"name":"Design, Automation and Test in Europe (DATE)","location":"Online"},"title":"MUSCAT: MUS-based Circuit Approximation Technique","year":"2022","status":"public","publication_status":"accepted","date_updated":"2022-02-22T07:52:01Z","date_created":"2022-02-16T16:22:23Z","department":[{"_id":"78"}],"type":"conference","citation":{"bibtex":"@inproceedings{Witschen_Wiersema_Artmann_Platzner, title={MUSCAT: MUS-based Circuit Approximation Technique}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Artmann, Matthias and Platzner, Marco} }","short":"L.M. Witschen, T. Wiersema, M. Artmann, M. Platzner, in: Design, Automation and Test in Europe (DATE), n.d.","ama":"Witschen LM, Wiersema T, Artmann M, Platzner M. MUSCAT: MUS-based Circuit Approximation Technique. In: <i>Design, Automation and Test in Europe (DATE)</i>.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Matthias Artmann, and Marco Platzner. “MUSCAT: MUS-Based Circuit Approximation Technique.” In <i>Design, Automation and Test in Europe (DATE)</i>, n.d.","ieee":"L. M. Witschen, T. Wiersema, M. Artmann, and M. Platzner, “MUSCAT: MUS-based Circuit Approximation Technique,” presented at the Design, Automation and Test in Europe (DATE), Online.","mla":"Witschen, Linus Matthias, et al. “MUSCAT: MUS-Based Circuit Approximation Technique.” <i>Design, Automation and Test in Europe (DATE)</i>.","apa":"Witschen, L. M., Wiersema, T., Artmann, M., &#38; Platzner, M. (n.d.). MUSCAT: MUS-based Circuit Approximation Technique. <i>Design, Automation and Test in Europe (DATE)</i>. Design, Automation and Test in Europe (DATE), Online."},"publication":"Design, Automation and Test in Europe (DATE)","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}]},{"status":"public","conference":{"location":"Madrid","start_date":"2022-04-20","name":"25th International Conference on Applications of Evolutionary Computation, EvoApplications 2022","end_date":"2022-04-22"},"user_id":"49992","volume":13224,"page":"386-401","publisher":"Springer International Publishing","_id":"30971","project":[{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"name":"SFB 901 - C2: SFB 901 - Subproject C2","_id":"14"},{"_id":"1","name":"SFB 901: SFB 901"}],"citation":{"chicago":"Hansmeier, Tim, and Marco Platzner. “Integrating Safety Guarantees into the Learning Classifier System XCS.” In <i>Applications of Evolutionary Computation, EvoApplications 2022, Proceedings</i>, 13224:386–401. Lecture Notes in Computer Science. Springer International Publishing, 2022. <a href=\"https://doi.org/10.1007/978-3-031-02462-7_25\">https://doi.org/10.1007/978-3-031-02462-7_25</a>.","short":"T. Hansmeier, M. Platzner, in: Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, Springer International Publishing, 2022, pp. 386–401.","apa":"Hansmeier, T., &#38; Platzner, M. (2022). Integrating Safety Guarantees into the Learning Classifier System XCS. <i>Applications of Evolutionary Computation, EvoApplications 2022, Proceedings</i>, <i>13224</i>, 386–401. <a href=\"https://doi.org/10.1007/978-3-031-02462-7_25\">https://doi.org/10.1007/978-3-031-02462-7_25</a>","ieee":"T. Hansmeier and M. Platzner, “Integrating Safety Guarantees into the Learning Classifier System XCS,” in <i>Applications of Evolutionary Computation, EvoApplications 2022, Proceedings</i>, Madrid, 2022, vol. 13224, pp. 386–401, doi: <a href=\"https://doi.org/10.1007/978-3-031-02462-7_25\">10.1007/978-3-031-02462-7_25</a>.","ama":"Hansmeier T, Platzner M. Integrating Safety Guarantees into the Learning Classifier System XCS. In: <i>Applications of Evolutionary Computation, EvoApplications 2022, Proceedings</i>. Vol 13224. Lecture Notes in Computer Science. Springer International Publishing; 2022:386-401. doi:<a href=\"https://doi.org/10.1007/978-3-031-02462-7_25\">10.1007/978-3-031-02462-7_25</a>","bibtex":"@inproceedings{Hansmeier_Platzner_2022, series={Lecture Notes in Computer Science}, title={Integrating Safety Guarantees into the Learning Classifier System XCS}, volume={13224}, DOI={<a href=\"https://doi.org/10.1007/978-3-031-02462-7_25\">10.1007/978-3-031-02462-7_25</a>}, booktitle={Applications of Evolutionary Computation, EvoApplications 2022, Proceedings}, publisher={Springer International Publishing}, author={Hansmeier, Tim and Platzner, Marco}, year={2022}, pages={386–401}, collection={Lecture Notes in Computer Science} }","mla":"Hansmeier, Tim, and Marco Platzner. “Integrating Safety Guarantees into the Learning Classifier System XCS.” <i>Applications of Evolutionary Computation, EvoApplications 2022, Proceedings</i>, vol. 13224, Springer International Publishing, 2022, pp. 386–401, doi:<a href=\"https://doi.org/10.1007/978-3-031-02462-7_25\">10.1007/978-3-031-02462-7_25</a>."},"date_updated":"2022-04-28T10:24:18Z","publication_status":"published","intvolume":"     13224","year":"2022","title":"Integrating Safety Guarantees into the Learning Classifier System XCS","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783031024610","9783031024627"]},"author":[{"id":"49992","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","first_name":"Tim","last_name":"Hansmeier"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"doi":"10.1007/978-3-031-02462-7_25","series_title":"Lecture Notes in Computer Science","language":[{"iso":"eng"}],"publication":"Applications of Evolutionary Computation, EvoApplications 2022, Proceedings","type":"conference","department":[{"_id":"78"}],"date_created":"2022-04-28T09:42:33Z"},{"date_created":"2022-08-16T09:58:34Z","type":"conference","department":[{"_id":"78"}],"publication":"2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","citation":{"mla":"Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support.” <i>2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)</i>, IEEE, 2022, pp. 120–27, doi:<a href=\"https://doi.org/10.1109/ipdpsw55747.2022.00029\">10.1109/ipdpsw55747.2022.00029</a>.","apa":"Clausing, L., &#38; Platzner, M. (2022). ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support. <i>2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)</i>, 120–127. <a href=\"https://doi.org/10.1109/ipdpsw55747.2022.00029\">https://doi.org/10.1109/ipdpsw55747.2022.00029</a>","ieee":"L. Clausing and M. Platzner, “ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support,” in <i>2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)</i>,  Lyon, France, 2022, pp. 120–127, doi: <a href=\"https://doi.org/10.1109/ipdpsw55747.2022.00029\">10.1109/ipdpsw55747.2022.00029</a>.","chicago":"Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support.” In <i>2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)</i>, 120–27. IEEE, 2022. <a href=\"https://doi.org/10.1109/ipdpsw55747.2022.00029\">https://doi.org/10.1109/ipdpsw55747.2022.00029</a>.","ama":"Clausing L, Platzner M. ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support. In: <i>2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)</i>. IEEE; 2022:120-127. doi:<a href=\"https://doi.org/10.1109/ipdpsw55747.2022.00029\">10.1109/ipdpsw55747.2022.00029</a>","short":"L. Clausing, M. Platzner, in: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–127.","bibtex":"@inproceedings{Clausing_Platzner_2022, title={ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support}, DOI={<a href=\"https://doi.org/10.1109/ipdpsw55747.2022.00029\">10.1109/ipdpsw55747.2022.00029</a>}, booktitle={2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, publisher={IEEE}, author={Clausing, Lennart and Platzner, Marco}, year={2022}, pages={120–127} }"},"project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"_id":"1","name":"SFB 901: SFB 901"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"}],"page":"120-127","publisher":"IEEE","_id":"32855","language":[{"iso":"eng"}],"user_id":"477","doi":"10.1109/ipdpsw55747.2022.00029","status":"public","title":"ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support","year":"2022","author":[{"id":"74287","last_name":"Clausing","first_name":"Lennart","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"publication_identifier":{"eisbn":["978-1-6654-9747-3"]},"conference":{"start_date":"2022-05-30","name":"2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","location":" Lyon, France","end_date":"2022-06-03"},"publication_status":"published","date_updated":"2022-11-18T09:36:00Z"},{"publication":"GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion","citation":{"mla":"Hansmeier, Tim, et al. “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion.” <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Association for Computing Machinery (ACM), 2022, pp. 2071–79, doi:<a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>.","ama":"Hansmeier T, Brede M, Platzner M. XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. In: <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>. Association for Computing Machinery (ACM); 2022:2071-2079. doi:<a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>","bibtex":"@inproceedings{Hansmeier_Brede_Platzner_2022, place={New York, NY, United States}, title={XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}, DOI={<a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>}, booktitle={GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Brede, Mathis and Platzner, Marco}, year={2022}, pages={2071–2079} }","apa":"Hansmeier, T., Brede, M., &#38; Platzner, M. (2022). XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 2071–2079. <a href=\"https://doi.org/10.1145/3520304.3533977\">https://doi.org/10.1145/3520304.3533977</a>","ieee":"T. Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion,” in <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Boston, MA, USA, 2022, pp. 2071–2079, doi: <a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>.","chicago":"Hansmeier, Tim, Mathis Brede, and Marco Platzner. “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion.” In <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 2071–79. New York, NY, United States: Association for Computing Machinery (ACM), 2022. <a href=\"https://doi.org/10.1145/3520304.3533977\">https://doi.org/10.1145/3520304.3533977</a>.","short":"T. Hansmeier, M. Brede, M. Platzner, in: GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2022, pp. 2071–2079."},"project":[{"name":"SFB 901: SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"}],"place":"New York, NY, United States","date_created":"2022-09-02T11:47:17Z","type":"conference","department":[{"_id":"78"}],"title":"XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion","year":"2022","status":"public","conference":{"start_date":"2022-07-09","name":"International Workshop on Learning Classifier Systems (IWLCS 2022)","location":"Boston, MA, USA","end_date":"2022-07-13"},"author":[{"orcid":"0000-0003-1377-3339","last_name":"Hansmeier","first_name":"Tim","full_name":"Hansmeier, Tim","id":"49992"},{"full_name":"Brede, Mathis","first_name":"Mathis","last_name":"Brede"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-11-18T10:13:22Z","publication_status":"published","page":"2071-2079","_id":"33253","language":[{"iso":"eng"}],"publisher":"Association for Computing Machinery (ACM)","doi":"10.1145/3520304.3533977","user_id":"477"}]