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Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–26. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2011, pp. 223–226, doi: <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>.","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–226. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2011, pp. 223–26, doi:<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>."},"quality_controlled":"1","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30","grant_number":"01|H11004A"}],"date_created":"2018-04-03T14:37:14Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"year":"2011","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","status":"public","author":[{"full_name":"Beisel, Tobias","last_name":"Beisel","first_name":"Tobias"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema","id":"3118"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"date_updated":"2023-09-26T13:43:48Z","page":"223-226","_id":"2193","language":[{"iso":"eng"}],"publisher":"IEEE Computer Society","doi":"10.1109/ASAP.2011.6043273","user_id":"15278"},{"has_accepted_license":"1","status":"public","user_id":"15278","ddc":["040"],"page":"55-60","_id":"656","publisher":"IEEE","quality_controlled":"1","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"file_date_updated":"2018-03-14T13:49:39Z","citation":{"apa":"Happe, M., Agne, A., &#38; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2011, pp. 55–60, doi: <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. IEEE, 2011. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>.","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2011, pp. 55–60, doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2011:55-60. doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }"},"date_updated":"2023-09-26T13:46:08Z","title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","year":"2011","author":[{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"}],"doi":"10.1109/ReConFig.2011.59","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"file_name":"656-2011_happe_reconfig.pdf","file_size":502244,"access_level":"closed","relation":"main_file","date_updated":"2018-03-14T13:49:39Z","file_id":"1220","content_type":"application/pdf","success":1,"creator":"florida","date_created":"2018-03-14T13:49:39Z"}],"date_created":"2017-10-17T12:42:59Z"},{"date_updated":"2023-09-26T13:45:04Z","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"author":[{"id":"3145","first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Michael","last_name":"Kauschke","full_name":"Kauschke, Michael"}],"title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","status":"public","year":"2011","user_id":"15278","doi":"10.1145/1950413.1950448","_id":"2200","language":[{"iso":"eng"}],"publisher":"ACM","page":"177-180","quality_controlled":"1","citation":{"apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }"},"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"type":"conference","date_created":"2018-04-03T15:08:13Z","place":"New York, NY, USA"},{"quality_controlled":"1","citation":{"bibtex":"@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }","ama":"Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int Journal of Recon- figurable Computing (IJRC)</i>. Published online 2011. doi:<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>","mla":"Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2011, doi:<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>, 2011. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011).","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” <i>Int. Journal of Recon- figurable Computing (IJRC)</i>, 2011, doi: <a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>.","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>"},"publication":"Int. Journal of Recon- figurable Computing (IJRC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","keyword":["funding-altera"],"date_created":"2018-04-03T15:09:49Z","date_updated":"2023-09-26T13:45:46Z","author":[{"full_name":"Schumacher, Tobias","last_name":"Schumacher","first_name":"Tobias"},{"last_name":"Süß","first_name":"Tim","full_name":"Süß, Tim"},{"id":"16153","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"status":"public","year":"2011","title":"FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study","user_id":"15278","doi":"10.1155/2011/760954","_id":"2201","language":[{"iso":"eng"}],"publisher":"Hindawi Publishing Corp."},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2018-04-03T15:05:52Z","quality_controlled":"1","citation":{"short":"M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–85. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">https://doi.org/10.1109/IPDPS.2011.153</a>.","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 2011, pp. 278–285, doi: <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>.","apa":"Grad, M., &#38; Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–285. <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">https://doi.org/10.1109/IPDPS.2011.153</a>","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>. IEEE Computer Society; 2011:278-285. doi:<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, IEEE Computer Society, 2011, pp. 278–85, doi:<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>."},"publication":"Proc. Reconfigurable Architectures Workshop (RAW)","doi":"10.1109/IPDPS.2011.153","user_id":"15278","language":[{"iso":"eng"}],"_id":"2198","publisher":"IEEE Computer Society","page":"278-285","date_updated":"2023-09-26T13:44:39Z","author":[{"first_name":"Mariusz","last_name":"Grad","full_name":"Grad, Mariusz"},{"id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian"}],"year":"2011","title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture","status":"public"},{"date_created":"2019-07-10T09:22:56Z","department":[{"_id":"78"}],"type":"journal_article","citation":{"ieee":"S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification,” <i>International Journal of Reconfigurable Computing</i>, vol. 2010, 2010.","apa":"Drzevitzky, S., Kastens, U., &#38; Platzner, M. (2010). Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. <i>International Journal of Reconfigurable Computing</i>, <i>2010</i>. <a href=\"https://doi.org/10.1155/2010/180242\">https://doi.org/10.1155/2010/180242</a>","chicago":"Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” <i>International Journal of Reconfigurable Computing</i> 2010 (2010). <a href=\"https://doi.org/10.1155/2010/180242\">https://doi.org/10.1155/2010/180242</a>.","short":"S. Drzevitzky, U. Kastens, M. Platzner, International Journal of Reconfigurable Computing 2010 (2010).","mla":"Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” <i>International Journal of Reconfigurable Computing</i>, vol. 2010, Hindawi Publishing Corporation, 2010, doi:<a href=\"https://doi.org/10.1155/2010/180242\">10.1155/2010/180242</a>.","bibtex":"@article{Drzevitzky_Kastens_Platzner_2010, title={Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}, volume={2010}, DOI={<a href=\"https://doi.org/10.1155/2010/180242\">10.1155/2010/180242</a>}, journal={International Journal of Reconfigurable Computing}, publisher={Hindawi Publishing Corporation}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2010} }","ama":"Drzevitzky S, Kastens U, Platzner M. Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. <i>International Journal of Reconfigurable Computing</i>. 2010;2010. doi:<a href=\"https://doi.org/10.1155/2010/180242\">10.1155/2010/180242</a>"},"publication":"International Journal of Reconfigurable Computing","publisher":"Hindawi Publishing Corporation","_id":"10605","language":[{"iso":"eng"}],"volume":2010,"doi":"10.1155/2010/180242","user_id":"3118","author":[{"full_name":"Drzevitzky, Stephanie","first_name":"Stephanie","last_name":"Drzevitzky"},{"last_name":"Kastens","first_name":"Uwe","full_name":"Kastens, Uwe"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"status":"public","year":"2010","title":"Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification","intvolume":"      2010","date_updated":"2022-01-06T06:50:47Z"},{"date_updated":"2022-01-06T06:50:47Z","year":"2010","title":"Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen","status":"public","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"}],"user_id":"3118","_id":"10614","publisher":"Paderborn University","language":[{"iso":"eng"}],"citation":{"bibtex":"@book{Agne_2010, title={Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}, publisher={Paderborn University}, author={Agne, Andreas}, year={2010} }","ama":"Agne A. <i>Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen</i>. 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Paderborn University."},"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T09:25:12Z"},{"_id":"10629","language":[{"iso":"eng"}],"publisher":"Paderborn University","alternative_title":["EMG-based Gait Analysis"],"user_id":"3118","author":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"}],"title":"EMG-basierte Ganganalyse","status":"public","year":"2010","date_updated":"2022-01-06T06:50:48Z","date_created":"2019-07-10T09:40:27Z","department":[{"_id":"78"}],"type":"mastersthesis","citation":{"ieee":"A. Boschmann, <i>EMG-basierte Ganganalyse</i>. Paderborn University, 2010.","apa":"Boschmann, A. (2010). <i>EMG-basierte Ganganalyse</i>. Paderborn University.","mla":"Boschmann, Alexander. <i>EMG-Basierte Ganganalyse</i>. Paderborn University, 2010.","bibtex":"@book{Boschmann_2010, title={EMG-basierte Ganganalyse}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2010} }","short":"A. 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