[{"publisher":"Paderborn University","author":[{"full_name":"Niklas, Jörg","first_name":"Jörg","last_name":"Niklas"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:48:29Z","user_id":"3118","title":"Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme","language":[{"iso":"eng"}],"year":"2008","citation":{"short":"J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme, Paderborn University, 2008.","ieee":"J. Niklas, Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University, 2008.","chicago":"Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008.","ama":"Niklas J. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University; 2008.","apa":"Niklas, J. (2008). Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University.","mla":"Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008.","bibtex":"@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }"},"type":"bachelorsthesis","date_updated":"2022-01-06T06:50:50Z","_id":"10718"},{"title":"Raytracing on a Custom Instruction Set CPU","user_id":"3118","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Marco","full_name":"Östermann, Marco","last_name":"Östermann"}],"date_created":"2019-07-10T11:52:51Z","status":"public","date_updated":"2022-01-06T06:50:50Z","_id":"10721","year":"2008","type":"bachelorsthesis","citation":{"short":"M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University, 2008.","ieee":"M. Östermann, Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.","apa":"Östermann, M. (2008). Raytracing on a Custom Instruction Set CPU. Paderborn University.","ama":"Östermann M. Raytracing on a Custom Instruction Set CPU. Paderborn University; 2008.","chicago":"Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.","bibtex":"@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }","mla":"Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008."},"language":[{"iso":"eng"}]},{"title":"Design and Evaluation of MicroBlaze Multi-core Architectures","user_id":"3118","date_created":"2019-07-10T12:03:01Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Westerheide","first_name":"Nico","full_name":"Westerheide, Nico"}],"_id":"10751","date_updated":"2022-01-06T06:50:50Z","citation":{"ieee":"N. Westerheide, Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University, 2008.","short":"N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures, Paderborn University, 2008.","mla":"Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008.","bibtex":"@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }","chicago":"Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008.","apa":"Westerheide, N. (2008). Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University.","ama":"Westerheide N. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University; 2008."},"type":"bachelorsthesis","year":"2008","language":[{"iso":"eng"}]},{"title":"A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic","user_id":"3118","extern":"1","status":"public","date_created":"2019-07-10T12:11:35Z","author":[{"first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","id":"61186"},{"first_name":"Hamed","full_name":"Tabkhi, Hamed","last_name":"Tabkhi"},{"last_name":"Miremadi","first_name":"Seyed Ghassem","full_name":"Miremadi, Seyed Ghassem"},{"first_name":"Alireza","full_name":"Ejlali, Alireza","last_name":"Ejlali"}],"publisher":"IEEE","department":[{"_id":"78"}],"publication":"2008 International Conference on Microelectronics","doi":"10.1109/ICM.2008.5393497","date_updated":"2022-01-06T06:50:50Z","_id":"10778","year":"2008","citation":{"short":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–447.","ieee":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic,” in 2008 International Conference on Microelectronics, 2008, pp. 444–447.","ama":"Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In: 2008 International Conference on Microelectronics. IEEE; 2008:444-447. doi:10.1109/ICM.2008.5393497","apa":"Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., & Ejlali, A. (2008). A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In 2008 International Conference on Microelectronics (pp. 444–447). IEEE. https://doi.org/10.1109/ICM.2008.5393497","chicago":"Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” In 2008 International Conference on Microelectronics, 444–47. IEEE, 2008. https://doi.org/10.1109/ICM.2008.5393497.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}, DOI={10.1109/ICM.2008.5393497}, booktitle={2008 International Conference on Microelectronics}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2008}, pages={444–447} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–47, doi:10.1109/ICM.2008.5393497."},"type":"conference","page":"444-447","language":[{"iso":"eng"}]},{"user_id":"398","title":"Realizing Reconfigurable Mesh Algorithms on Softcore Arrays","status":"public","date_created":"2019-10-04T22:05:22Z","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","publication":"Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)","department":[{"_id":"78"}],"date_updated":"2022-01-06T06:51:40Z","_id":"13629","language":[{"iso":"eng"}],"type":"conference","citation":{"short":"H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.","ieee":"H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), 2008.","apa":"Giefers, H., & Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE.","ama":"Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE; 2008.","chicago":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE, 2008.","bibtex":"@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2008} }","mla":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008."},"year":"2008"},{"user_id":"398","title":"Communication and Synchronization in Multithreaded Reconfigurable Computing Systems","publisher":"CSREA Press","author":[{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","date_created":"2019-10-04T22:07:14Z","_id":"13630","date_updated":"2022-01-06T06:51:40Z","language":[{"iso":"eng"}],"year":"2008","type":"conference","citation":{"ieee":"E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008.","short":"E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","mla":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.","ama":"Lübbers E, Platzner M. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008.","apa":"Lübbers, E., & Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","chicago":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2008."}},{"date_updated":"2022-01-06T06:51:40Z","_id":"13631","doi":"10.1109/fpl.2008.4629901","language":[{"iso":"eng"}],"year":"2008","citation":{"short":"E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.","ieee":"E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,” in Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), 2008.","chicago":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. https://doi.org/10.1109/fpl.2008.4629901.","apa":"Lübbers, E., & Platzner, M. (2008). A portable abstraction layer for hardware threads. In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2008.4629901","ama":"Lübbers E, Platzner M. A portable abstraction layer for hardware threads. In: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2008. doi:10.1109/fpl.2008.4629901","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer for hardware threads}, DOI={10.1109/fpl.2008.4629901}, booktitle={Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","mla":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008, doi:10.1109/fpl.2008.4629901."},"type":"conference","user_id":"398","title":"A portable abstraction layer for hardware threads","publisher":"IEEE","author":[{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)","status":"public","date_created":"2019-10-04T22:07:43Z","publication_status":"published","publication_identifier":{"isbn":["9781424419609"]}},{"user_id":"15278","title":"A Hardware Accelerator for k-th Nearest Neighbor Thinning","date_created":"2018-04-17T11:33:32Z","status":"public","publication_identifier":{"isbn":["1-60132-064-7"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"last_name":"Meiche","first_name":"Robert","full_name":"Meiche, Robert"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"CSREA Press","quality_controlled":"1","date_updated":"2023-09-26T13:54:24Z","_id":"2364","language":[{"iso":"eng"}],"page":"245-251","citation":{"short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","ieee":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.","chicago":"Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008.","apa":"Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., & Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–251.","ama":"Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.","bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51."},"year":"2008","type":"conference"},{"user_id":"15278","title":"IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers","date_created":"2018-04-17T12:05:28Z","status":"public","keyword":["IMORC","IP core","interconnect"],"publication":"Many-core and Reconfigurable Supercomputing Conference (MRSC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","date_updated":"2023-09-26T13:55:51Z","_id":"2372","language":[{"iso":"eng"}],"citation":{"short":"T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: Many-Core and Reconfigurable Supercomputing Conference (MRSC). ; 2008.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. Many-Core and Reconfigurable Supercomputing Conference (MRSC).","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }"},"year":"2008","type":"conference"},{"status":"public","date_created":"2019-01-08T09:52:43Z","publisher":"IEEE","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"user_id":"3118","abstract":[{"lang":"eng","text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits."}],"type":"conference","year":"2007","citation":{"ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, UK, 2007, pp. 447–454.","short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.","mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={10.1109/ahs.2007.73}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }","apa":"Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007). IEEE; 2007:447-454. doi:10.1109/ahs.2007.73","chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73."},"page":"447-454","_id":"6508","conference":{"start_date":"2007-08-05","name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","location":"Edinburgh, UK","end_date":"2007-08-08"},"publication_status":"published","publication_identifier":{"isbn":["076952866X","9780769528663"]},"department":[{"_id":"78"}],"title":"MOVES: A Modular Framework for Hardware Evolution","language":[{"iso":"eng"}],"doi":"10.1109/ahs.2007.73","date_updated":"2022-01-06T07:03:08Z"},{"language":[{"iso":"eng"}],"year":"2007","citation":{"short":"T. Beisel, Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen, Paderborn University, 2007.","ieee":"T. Beisel, Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University, 2007.","ama":"Beisel T. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University; 2007.","apa":"Beisel, T. (2007). Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University.","chicago":"Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007.","bibtex":"@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }","mla":"Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007."},"type":"mastersthesis","date_updated":"2022-01-06T06:50:48Z","_id":"10623","publisher":"Paderborn University","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T09:36:57Z","user_id":"3118","title":"Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen"},{"user_id":"398","title":"Dynamically Reconfigurable Architectures (editorial)","date_created":"2019-07-10T09:40:11Z","status":"public","volume":2007,"department":[{"_id":"78"}],"publication":"{EURASIP} Journal on Embedded Systems","publisher":"Springer Science+Business Media","author":[{"last_name":"Bergmann","full_name":"Bergmann, Neil","first_name":"Neil"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Teich, Jürgen","first_name":"Jürgen","last_name":"Teich"}],"doi":"10.1155/2007/28405","intvolume":" 2007","_id":"10625","date_updated":"2022-01-06T06:50:48Z","language":[{"iso":"eng"}],"page":"1-2","citation":{"short":"N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems 2007 (2007) 1–2.","ieee":"N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” {EURASIP} Journal on Embedded Systems, vol. 2007, pp. 1–2, 2007.","ama":"Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems. 2007;2007:1-2. doi:10.1155/2007/28405","apa":"Bergmann, N., Platzner, M., & Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems, 2007, 1–2. https://doi.org/10.1155/2007/28405","chicago":"Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems 2007 (2007): 1–2. https://doi.org/10.1155/2007/28405.","bibtex":"@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={10.1155/2007/28405}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }","mla":"Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:10.1155/2007/28405."},"type":"journal_article","year":"2007"},{"_id":"10643","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"}],"citation":{"short":"T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim, Paderborn University, 2007.","ieee":"T. Ceylan and C. Yalcin, Distributed Simulation of mobile Robots using EyeSim. Paderborn University, 2007.","chicago":"Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007.","apa":"Ceylan, T., & Yalcin, C. (2007). Distributed Simulation of mobile Robots using EyeSim. Paderborn University.","ama":"Ceylan T, Yalcin C. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University; 2007.","bibtex":"@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }","mla":"Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007."},"type":"bachelorsthesis","year":"2007","user_id":"3118","title":"Distributed Simulation of mobile Robots using EyeSim","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"first_name":"Toni","full_name":"Ceylan, Toni","last_name":"Ceylan"},{"last_name":"Yalcin","first_name":"Coni","full_name":"Yalcin, Coni"}],"date_created":"2019-07-10T11:03:44Z","status":"public"},{"issue":"4","doi":"10.1049/iet-cdt:20060186","_id":"10646","intvolume":" 1","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"page":"295-302","year":"2007","type":"journal_article","citation":{"short":"K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.","ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007.","ama":"Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques. 2007;1(4):295-302. doi:10.1049/iet-cdt:20060186","apa":"Danne, K., Mühlenbernd, R., & Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques, 1(4), 295–302. https://doi.org/10.1049/iet-cdt:20060186","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques 1, no. 4 (2007): 295–302. https://doi.org/10.1049/iet-cdt:20060186.","mla":"Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques, vol. 1, no. 4, 2007, pp. 295–302, doi:10.1049/iet-cdt:20060186.","bibtex":"@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={10.1049/iet-cdt:20060186}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }"},"user_id":"3118","title":"Server-based execution of periodic tasks on dynamically reconfigurable hardware","date_created":"2019-07-10T11:10:54Z","status":"public","publication_identifier":{"issn":["1751-8601"]},"volume":1,"department":[{"_id":"78"}],"keyword":["reconfigurable architectures","resource allocation","device reconfiguration time","dynamic hardware reconfiguration","dynamically reconfigurable hardware","light-weight runtime system","merge server distribute load","periodic real-time tasks","runtime system overheads","schedulability analysis","scheduling technique","server-based execution","synthesis tool flow"],"publication":"IET Computers Digital Techniques","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Mühlenbernd","first_name":"Roland","full_name":"Mühlenbernd, Roland"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}]},{"author":[{"first_name":"Bertrand","full_name":"Defo, Bertrand","last_name":"Defo"}],"publisher":"Paderborn University","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:10:55Z","user_id":"3118","title":"A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization","supervisor":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"type":"mastersthesis","year":"2007","citation":{"bibtex":"@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }","mla":"Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","ama":"Defo B. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University; 2007.","apa":"Defo, B. (2007). A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University.","chicago":"Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","ieee":"B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.","short":"B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization, Paderborn University, 2007."},"date_updated":"2022-01-06T06:50:49Z","_id":"10647"},{"date_created":"2019-07-10T11:10:56Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Döhre","first_name":"Sven","full_name":"Döhre, Sven"}],"user_id":"3118","title":"Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme","language":[{"iso":"eng"}],"year":"2007","type":"mastersthesis","citation":{"bibtex":"@book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University}, author={Döhre, Sven}, year={2007} }","mla":"Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007.","chicago":"Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007.","ama":"Döhre S. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University; 2007.","apa":"Döhre, S. (2007). Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University.","ieee":"S. Döhre, Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University, 2007.","short":"S. Döhre, Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme, Paderborn University, 2007."},"date_updated":"2022-01-06T06:50:49Z","_id":"10648"},{"_id":"10689","date_updated":"2022-01-06T06:50:49Z","intvolume":" 4415","page":"199-208","year":"2007","citation":{"mla":"Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” Architecture of Computing Systems (ARCS), vol. 4415, Springer, 2007, pp. 199–208.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, series={LNCS}, title={Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution}, volume={4415}, booktitle={Architecture of Computing Systems (ARCS)}, publisher={Springer}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={199–208}, collection={LNCS} }","ama":"Kaufmann P, Platzner M. Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In: Architecture of Computing Systems (ARCS). Vol 4415. LNCS. Springer; 2007:199-208.","apa":"Kaufmann, P., & Platzner, M. (2007). Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In Architecture of Computing Systems (ARCS) (Vol. 4415, pp. 199–208). Springer.","chicago":"Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” In Architecture of Computing Systems (ARCS), 4415:199–208. LNCS. Springer, 2007.","ieee":"P. Kaufmann and M. Platzner, “Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution,” in Architecture of Computing Systems (ARCS), 2007, vol. 4415, pp. 199–208.","short":"P. Kaufmann, M. Platzner, in: Architecture of Computing Systems (ARCS), Springer, 2007, pp. 199–208."},"type":"conference","language":[{"iso":"eng"}],"series_title":"LNCS","title":"Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution","user_id":"3118","volume":4415,"date_created":"2019-07-10T11:29:03Z","status":"public","publication":"Architecture of Computing Systems (ARCS)","department":[{"_id":"78"}],"publisher":"Springer","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}]},{"_id":"10709","date_updated":"2022-01-06T06:50:50Z","supervisor":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","year":"2007","citation":{"ieee":"R. Meiche, VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.","short":"R. Meiche, VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen, Paderborn University, 2007.","bibtex":"@book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University}, author={Meiche, Robert}, year={2007} }","mla":"Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.","apa":"Meiche, R. (2007). VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University.","ama":"Meiche R. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University; 2007.","chicago":"Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007."},"user_id":"3118","title":"VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen","date_created":"2019-07-10T11:43:33Z","status":"public","alternative_title":["k-th Nearest Neighbor VHDL- Implementation for Multi-objective Algorithm Diversity-preserving Mechanism Acceleration"],"department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Meiche, Robert","first_name":"Robert","last_name":"Meiche"}]},{"user_id":"3118","title":"Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS","publisher":"Paderborn University","author":[{"full_name":"Reisch, Waldemar","first_name":"Waldemar","last_name":"Reisch"}],"department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:54:46Z","date_updated":"2022-01-06T06:50:50Z","_id":"10728","language":[{"iso":"eng"}],"citation":{"chicago":"Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.","ama":"Reisch W. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University; 2007.","apa":"Reisch, W. (2007). Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University.","bibtex":"@book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University}, author={Reisch, Waldemar}, year={2007} }","mla":"Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.","short":"W. Reisch, Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS, Paderborn University, 2007.","ieee":"W. Reisch, Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007."},"year":"2007","type":"mastersthesis"},{"date_updated":"2022-01-06T06:50:50Z","_id":"10729","year":"2007","citation":{"bibtex":"@book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn University}, author={Rethmeier, Eike}, year={2007} }","mla":"Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007.","ama":"Rethmeier E. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University; 2007.","apa":"Rethmeier, E. (2007). Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University.","chicago":"Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007.","ieee":"E. Rethmeier, Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University, 2007.","short":"E. Rethmeier, Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem, Paderborn University, 2007."},"type":"mastersthesis","language":[{"iso":"eng"}],"title":"Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem","user_id":"3118","date_created":"2019-07-10T11:54:47Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Rethmeier","full_name":"Rethmeier, Eike","first_name":"Eike"}],"publisher":"Paderborn University"}]