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IEEE, 2009. <a href=\"https://doi.org/10.1109/PRDC.2009.69\">https://doi.org/10.1109/PRDC.2009.69</a>.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Miremadi_Ejlali_2009, title={Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors}, DOI={<a href=\"https://doi.org/10.1109/PRDC.2009.69\">10.1109/PRDC.2009.69</a>}, booktitle={Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2009}, pages={252–255} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.” <i>Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On</i>, IEEE, 2009, pp. 252–55, doi:<a href=\"https://doi.org/10.1109/PRDC.2009.69\">10.1109/PRDC.2009.69</a>.","apa":"Ghasemzadeh Mohammadi, H., Miremadi, S. G., &#38; Ejlali, A. (2009). Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In <i>Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on</i> (pp. 252–255). IEEE. <a href=\"https://doi.org/10.1109/PRDC.2009.69\">https://doi.org/10.1109/PRDC.2009.69</a>","ieee":"H. Ghasemzadeh Mohammadi, S. G. Miremadi, and A. Ejlali, “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors,” in <i>Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on</i>, 2009, pp. 252–255."},"publication":"Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on","extern":"1","date_created":"2019-07-10T12:11:34Z","department":[{"_id":"78"}],"type":"conference","author":[{"last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","full_name":"Ghasemzadeh Mohammadi, Hassan","id":"61186"},{"full_name":"Miremadi, Seyed Ghassem","first_name":"Seyed Ghassem","last_name":"Miremadi"},{"first_name":"Alireza","last_name":"Ejlali","full_name":"Ejlali, Alireza"}],"title":"Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors","status":"public","year":"2009","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"_id":"10777","publisher":"IEEE","page":"252-255","doi":"10.1109/PRDC.2009.69","user_id":"3118"},{"author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"title":"A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms","status":"public","year":"2009","date_updated":"2022-01-06T06:51:40Z","publisher":"Springer","_id":"13632","language":[{"iso":"eng"}],"user_id":"398","citation":{"bibtex":"@inproceedings{Happe_Lübbers_Platzner_2009, title={A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms}, booktitle={Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }","ama":"Happe M, Lübbers E, Platzner M. A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In: <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer; 2009.","mla":"Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, Springer, 2009.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer, 2009.","short":"M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.","ieee":"M. Happe, E. Lübbers, and M. Platzner, “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms,” in <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2009.","apa":"Happe, M., Lübbers, E., &#38; Platzner, M. (2009). A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer."},"publication":"Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)","date_created":"2019-10-04T22:13:24Z","department":[{"_id":"78"}],"type":"conference"},{"publication":"Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)","citation":{"apa":"Giefers, H., &#38; Platzner, M. (2009). Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>.","ieee":"H. Giefers and M. Platzner, “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh,” in <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>, 2009.","chicago":"Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” In <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>, 2009.","short":"H. Giefers, M. Platzner, in: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.","mla":"Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>, 2009.","ama":"Giefers H, Platzner M. Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In: <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>. ; 2009.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={Towards Models for Many-Cores: The Case for the Reconfigurable Mesh}, booktitle={Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }"},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T22:16:01Z","date_updated":"2022-01-06T06:51:40Z","title":"Towards Models for Many-Cores: The Case for the Reconfigurable Mesh","status":"public","year":"2009","author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"user_id":"398","_id":"13634","language":[{"iso":"eng"}]},{"_id":"13635","language":[{"iso":"eng"}],"publisher":"IEEE","user_id":"398","status":"public","year":"2009","title":"ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores","author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T22:17:57Z","type":"conference","department":[{"_id":"78"}],"publication":"Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium","citation":{"mla":"Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>, IEEE, 2009.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores}, booktitle={Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }","ama":"Giefers H, Platzner M. ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In: <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>. IEEE; 2009.","ieee":"H. Giefers and M. Platzner, “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores,” in <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>, 2009.","apa":"Giefers, H., &#38; Platzner, M. (2009). ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>. IEEE.","chicago":"Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” In <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>. IEEE, 2009.","short":"H. Giefers, M. Platzner, in: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009."}},{"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T22:20:12Z","publication":"Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ","citation":{"ieee":"E. Lübbers and M. Platzner, “Cooperative Multithreading in Dynamically Reconfigurable Systems,” in <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, 2009.","apa":"Lübbers, E., &#38; Platzner, M. (2009). Cooperative Multithreading in Dynamically Reconfigurable Systems. In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE.","short":"E. Lübbers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","chicago":"Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE, 2009.","mla":"Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, IEEE, 2009.","bibtex":"@inproceedings{Lübbers_Platzner_2009, title={Cooperative Multithreading in Dynamically Reconfigurable Systems}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2009} }","ama":"Lübbers E, Platzner M. Cooperative Multithreading in Dynamically Reconfigurable Systems. In: <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE; 2009."},"user_id":"398","_id":"13636","publisher":"IEEE","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:40Z","title":"Cooperative Multithreading in Dynamically Reconfigurable Systems","status":"public","year":"2009","author":[{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}]},{"language":[{"iso":"eng"}],"_id":"13637","publisher":"IEEE","user_id":"398","status":"public","year":"2009","title":"Program-driven Fine-grained Power Management for the Reconfigurable Mesh","author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T22:22:02Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ","citation":{"bibtex":"@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }","chicago":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE, 2009.","ama":"Giefers H, Platzner M. Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In: <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE; 2009.","short":"H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","ieee":"H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management for the Reconfigurable Mesh,” in <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, 2009.","mla":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, IEEE, 2009.","apa":"Giefers, H., &#38; Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE."}},{"publication":"Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)","citation":{"apa":"Happe, M., Lübbers, E., &#38; Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>. IEEE. <a href=\"https://doi.org/10.1109/fpt.2009.5377645\">https://doi.org/10.1109/fpt.2009.5377645</a>","ieee":"M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning,” in <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>, 2009.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” In <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>. IEEE, 2009. <a href=\"https://doi.org/10.1109/fpt.2009.5377645\">https://doi.org/10.1109/fpt.2009.5377645</a>.","short":"M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009.","mla":"Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2009, doi:<a href=\"https://doi.org/10.1109/fpt.2009.5377645\">10.1109/fpt.2009.5377645</a>.","ama":"Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In: <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2009. doi:<a href=\"https://doi.org/10.1109/fpt.2009.5377645\">10.1109/fpt.2009.5377645</a>","bibtex":"@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}, DOI={<a href=\"https://doi.org/10.1109/fpt.2009.5377645\">10.1109/fpt.2009.5377645</a>}, booktitle={Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }"},"date_created":"2019-10-04T22:22:52Z","type":"conference","department":[{"_id":"78"}],"status":"public","year":"2009","title":"An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning","publication_identifier":{"isbn":["9781424443758"]},"author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:51:40Z","publication_status":"published","publisher":"IEEE","_id":"13638","language":[{"iso":"eng"}],"doi":"10.1109/fpt.2009.5377645","user_id":"398"},{"citation":{"mla":"Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2009.","ama":"Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2009.","bibtex":"@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2009} }","apa":"Drzevitzky, S., Kastens, U., &#38; Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE.","ieee":"S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009.","chicago":"Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE, 2009.","short":"S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009."},"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"type":"conference","date_created":"2019-10-04T22:25:10Z","date_updated":"2022-01-06T06:51:40Z","author":[{"full_name":"Drzevitzky, Stephanie","first_name":"Stephanie","last_name":"Drzevitzky"},{"last_name":"Kastens","first_name":"Uwe","full_name":"Kastens, Uwe"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"year":"2009","status":"public","title":"Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules","user_id":"398","publisher":"IEEE","_id":"13639","language":[{"iso":"eng"}]},{"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"date_created":"2018-04-16T15:05:52Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["IMORC","interconnect","performance"],"author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"publication_identifier":{"isbn":["978-1-4244-4450-2"]},"year":"2009","title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","date_updated":"2023-09-26T13:51:44Z","language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2009.25","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2009, pp. 275–278, doi: <a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–278. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2009, pp. 275–78, doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–78. IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2009:275-278. doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>"},"quality_controlled":"1","status":"public","_id":"2350","publisher":"IEEE Computer Society","page":"275-278","user_id":"15278"},{"date_created":"2018-04-06T15:18:24Z","place":"Los Alamitos, CA, USA","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["EvoCache","evolvable hardware","computer architecture"],"citation":{"chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 2009, pp. 11–18.","apa":"Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>. IEEE Computer Society; 2009:11-18.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, IEEE Computer Society, 2009, pp. 11–18."},"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","quality_controlled":"1","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"_id":"2262","language":[{"iso":"eng"}],"publisher":"IEEE Computer Society","page":"11-18","user_id":"15278","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"id":"16153","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"year":"2009","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","status":"public","date_updated":"2023-09-26T13:53:11Z"},{"publisher":"IEEE Computer Society","_id":"2238","language":[{"iso":"eng"}],"page":"119-124","doi":"10.1109/ReConFig.2009.32","user_id":"15278","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"full_name":"Süß, Tim","last_name":"Süß","first_name":"Tim"},{"full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","status":"public","year":"2009","date_updated":"2023-09-26T13:52:32Z","place":"Los Alamitos, CA, USA","date_created":"2018-04-05T17:11:28Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["IMORC","graphics"],"citation":{"bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2009:119-124. doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2009, pp. 119–24, doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009, pp. 119–124, doi: <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–124. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>"},"publication":"Proc. Int. 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Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2009:338-344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–44. IEEE, 2009.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2009, pp. 338–44.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2009, pp. 338–344."},"publication":"Proc. Int. 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Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2009, pp. 319–22.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2009:319-322.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","apa":"Grad, M., &#38; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–322.","ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2009, pp. 319–322.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–22. USA: CSREA Press, 2009."},"abstract":[{"text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. ","lang":"eng"}],"quality_controlled":"1","date_created":"2018-04-06T15:19:51Z","place":"USA","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"publication":"IEEE Nuclear Science Symposium Conference Record (NSS)","citation":{"short":"T. Beisel, S. Lietsch, K. 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IEEE. <a href=\"https://doi.org/10.1109/NSSMIC.2008.4774198\">https://doi.org/10.1109/NSSMIC.2008.4774198</a>","bibtex":"@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM PET reconstruction on parallel architectures using STIR}, DOI={<a href=\"https://doi.org/10.1109/NSSMIC.2008.4774198\">10.1109/NSSMIC.2008.4774198</a>}, booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE}, author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008}, pages={4161–4168} }","ama":"Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on parallel architectures using STIR. In: <i>IEEE Nuclear Science Symposium Conference Record (NSS)</i>. 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The GOmputer: Accelerating GO with FPGAs. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008:245-251.","bibtex":"@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008, title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}, year={2008}, pages={245–251} }","mla":"Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008, pp. 245–51.","short":"M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","chicago":"Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating GO with FPGAs.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.","apa":"Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T., … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 245–251). CSREA Press.","ieee":"M. Platzner <i>et al.</i>, “The GOmputer: Accelerating GO with FPGAs,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008, pp. 245–251."},"publication":"Proc. Int. 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Paderborn University, 2008.","chicago":"Breitlauch, Daniel. <i>Selbstoptimierender Cache-Kontroller</i>. Paderborn University, 2008.","short":"D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University, 2008.","ama":"Breitlauch D. <i>Selbstoptimierender Cache-Kontroller</i>. Paderborn University; 2008.","bibtex":"@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2008} }"},"type":"bachelorsthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T11:03:42Z","date_updated":"2022-01-06T06:50:49Z","title":"Selbstoptimierender Cache-Kontroller","status":"public","year":"2008","author":[{"last_name":"Breitlauch","first_name":"Daniel","full_name":"Breitlauch, Daniel"}],"user_id":"3118","alternative_title":["Self-optimizing Cache Controller"],"language":[{"iso":"eng"}],"_id":"10641","publisher":"Paderborn University"},{"citation":{"short":"T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim, Paderborn University, 2008.","chicago":"Ceylan, Toni, and Coni Yalcin. <i>Verteilte Simulation von Mobilen Robotern Mit EyeSim</i>. Paderborn University, 2008.","ieee":"T. Ceylan and C. Yalcin, <i>Verteilte Simulation von mobilen Robotern mit EyeSim</i>. Paderborn University, 2008.","apa":"Ceylan, T., &#38; Yalcin, C. (2008). <i>Verteilte Simulation von mobilen Robotern mit EyeSim</i>. Paderborn University.","bibtex":"@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2008} }","ama":"Ceylan T, Yalcin C. <i>Verteilte Simulation von Mobilen Robotern Mit EyeSim</i>. Paderborn University; 2008.","mla":"Ceylan, Toni, and Coni Yalcin. <i>Verteilte Simulation von Mobilen Robotern Mit EyeSim</i>. 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IEEE; 2008:32-39.","bibtex":"@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }"},"publication":"IEEE Adaptive Hardware and Systems (AHS)","date_created":"2019-07-10T11:13:13Z","department":[{"_id":"78"}],"type":"conference","author":[{"full_name":"Glette, Kyrre","last_name":"Glette","first_name":"Kyrre"},{"full_name":"Gruber, Thiemo","first_name":"Thiemo","last_name":"Gruber"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"},{"full_name":"Sick, Bernhard","last_name":"Sick","first_name":"Bernhard"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"status":"public","title":"Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control","year":"2008","date_updated":"2022-01-06T06:50:49Z","publisher":"IEEE","_id":"10653","language":[{"iso":"eng"}],"page":"32-39","user_id":"3118"},{"date_updated":"2022-01-06T06:50:49Z","intvolume":"      5216","title":"A Comparison of Evolvable Hardware Architectures for Classification Tasks","year":"2008","status":"public","author":[{"first_name":"Kyrre","last_name":"Glette","full_name":"Glette, Kyrre"},{"full_name":"Torresen, Jim","last_name":"Torresen","first_name":"Jim"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"user_id":"3118","volume":5216,"page":"22-33","publisher":"Springer","_id":"10656","series_title":"LNCS","language":[{"iso":"eng"}],"publication":"IEEE Intl. Conf. on Evolvable Systems (ICES)","citation":{"apa":"Glette, K., Torresen, J., Kaufmann, P., &#38; Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i> (Vol. 5216, pp. 22–33). Springer.","ieee":"K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable Hardware Architectures for Classification Tasks,” in <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, 2008, vol. 5216, pp. 22–33.","chicago":"Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” In <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, 5216:22–33. LNCS. Springer, 2008.","short":"K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. 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