[{"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T11:15:14Z","citation":{"ama":"Happe M. <i>Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern</i>. Paderborn University; 2008.","bibtex":"@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus}, year={2008} }","mla":"Happe, Markus. <i>Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern</i>. Paderborn University, 2008.","chicago":"Happe, Markus. <i>Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern</i>. Paderborn University, 2008.","short":"M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern, Paderborn University, 2008.","apa":"Happe, M. (2008). <i>Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern</i>. Paderborn University.","ieee":"M. Happe, <i>Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern</i>. Paderborn University, 2008."},"user_id":"3118","_id":"10669","language":[{"iso":"eng"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","year":"2008","status":"public","title":"Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern","author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"}]},{"date_created":"2019-07-10T11:29:14Z","type":"preprint","department":[{"_id":"78"}],"citation":{"apa":"Torresen, J., Glette, K., Platzner, M., &#38; Kaufmann, P. (2008). Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).","ieee":"J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).” 2008.","short":"J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008).","chicago":"Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008.","mla":"Torresen, Jim, et al. <i>Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)</i>. 2008.","ama":"Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008.","bibtex":"@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }"},"_id":"10690","language":[{"iso":"eng"}],"user_id":"398","title":"Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)","status":"public","year":"2008","author":[{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"},{"last_name":"Glette","first_name":"Kyrre","full_name":"Glette, Kyrre"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"date_updated":"2022-01-06T06:50:49Z"},{"publication":"Genetic and Evolutionary Computation (GECCO)","citation":{"apa":"Kaufmann, P., &#38; Platzner, M. (2008). Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In <i>Genetic and Evolutionary Computation (GECCO)</i> (pp. 1219–1226). ACM Press.","ieee":"P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming,” in <i>Genetic and Evolutionary Computation (GECCO)</i>, 2008, pp. 1219–1226.","chicago":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” In <i>Genetic and Evolutionary Computation (GECCO)</i>, 1219–26. ACM Press, 2008.","short":"P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–1226.","mla":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” <i>Genetic and Evolutionary Computation (GECCO)</i>, ACM Press, 2008, pp. 1219–26.","ama":"Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In: <i>Genetic and Evolutionary Computation (GECCO)</i>. ACM Press; 2008:1219-1226.","bibtex":"@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }"},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T11:29:57Z","date_updated":"2022-01-06T06:50:49Z","title":"Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming","status":"public","year":"2008","author":[{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"user_id":"3118","page":"1219 - 1226","language":[{"iso":"eng"}],"_id":"10691","publisher":"ACM Press"},{"title":"Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf","year":"2008","status":"public","author":[{"full_name":"Knieper, Tobias","last_name":"Knieper","first_name":"Tobias"}],"date_updated":"2022-01-06T06:50:49Z","publisher":"Paderborn University","_id":"10696","language":[{"iso":"eng"}],"user_id":"3118","alternative_title":["Multi-objective Optimizer IBEA for Digital Logic Design"],"citation":{"short":"T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008.","chicago":"Knieper, Tobias. <i>Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf</i>. Paderborn University, 2008.","apa":"Knieper, T. (2008). <i>Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf</i>. Paderborn University.","ieee":"T. Knieper, <i>Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf</i>. Paderborn University, 2008.","ama":"Knieper T. <i>Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf</i>. Paderborn University; 2008.","bibtex":"@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2008} }","mla":"Knieper, Tobias. <i>Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf</i>. Paderborn University, 2008."},"supervisor":[{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"}],"date_created":"2019-07-10T11:30:22Z","type":"bachelorsthesis","department":[{"_id":"78"}]},{"author":[{"last_name":"Niklas","first_name":"Jörg","full_name":"Niklas, Jörg"}],"title":"Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme","year":"2008","status":"public","date_updated":"2022-01-06T06:50:50Z","publisher":"Paderborn University","_id":"10718","language":[{"iso":"eng"}],"user_id":"3118","citation":{"short":"J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme, Paderborn University, 2008.","chicago":"Niklas, Jörg. <i>Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme</i>. Paderborn University, 2008.","apa":"Niklas, J. (2008). <i>Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme</i>. Paderborn University.","ieee":"J. Niklas, <i>Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme</i>. Paderborn University, 2008.","ama":"Niklas J. <i>Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme</i>. Paderborn University; 2008.","bibtex":"@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }","mla":"Niklas, Jörg. <i>Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme</i>. Paderborn University, 2008."},"date_created":"2019-07-10T11:48:29Z","department":[{"_id":"78"}],"type":"bachelorsthesis"},{"department":[{"_id":"78"}],"type":"bachelorsthesis","date_created":"2019-07-10T11:52:51Z","citation":{"chicago":"Östermann, Marco. <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn University, 2008.","short":"M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University, 2008.","apa":"Östermann, M. (2008). <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn University.","ieee":"M. Östermann, <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn University, 2008.","ama":"Östermann M. <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn University; 2008.","bibtex":"@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }","mla":"Östermann, Marco. <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn University, 2008."},"user_id":"3118","language":[{"iso":"eng"}],"_id":"10721","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","author":[{"first_name":"Marco","last_name":"Östermann","full_name":"Östermann, Marco"}],"year":"2008","title":"Raytracing on a Custom Instruction Set CPU","status":"public"},{"language":[{"iso":"eng"}],"_id":"10751","publisher":"Paderborn University","user_id":"3118","status":"public","year":"2008","title":"Design and Evaluation of MicroBlaze Multi-core Architectures","author":[{"first_name":"Nico","last_name":"Westerheide","full_name":"Westerheide, Nico"}],"date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:03:01Z","type":"bachelorsthesis","department":[{"_id":"78"}],"citation":{"apa":"Westerheide, N. (2008). <i>Design and Evaluation of MicroBlaze Multi-core Architectures</i>. Paderborn University.","mla":"Westerheide, Nico. <i>Design and Evaluation of MicroBlaze Multi-Core Architectures</i>. Paderborn University, 2008.","ieee":"N. Westerheide, <i>Design and Evaluation of MicroBlaze Multi-core Architectures</i>. Paderborn University, 2008.","ama":"Westerheide N. <i>Design and Evaluation of MicroBlaze Multi-Core Architectures</i>. Paderborn University; 2008.","short":"N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures, Paderborn University, 2008.","chicago":"Westerheide, Nico. <i>Design and Evaluation of MicroBlaze Multi-Core Architectures</i>. Paderborn University, 2008.","bibtex":"@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }"}},{"user_id":"3118","doi":"10.1109/ICM.2008.5393497","_id":"10778","publisher":"IEEE","language":[{"iso":"eng"}],"page":"444-447","date_updated":"2022-01-06T06:50:50Z","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","id":"61186"},{"last_name":"Tabkhi","first_name":"Hamed","full_name":"Tabkhi, Hamed"},{"last_name":"Miremadi","first_name":"Seyed Ghassem","full_name":"Miremadi, Seyed Ghassem"},{"first_name":"Alireza","last_name":"Ejlali","full_name":"Ejlali, Alireza"}],"title":"A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic","status":"public","year":"2008","department":[{"_id":"78"}],"type":"conference","date_created":"2019-07-10T12:11:35Z","extern":"1","citation":{"ieee":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic,” in <i>2008 International Conference on Microelectronics</i>, 2008, pp. 444–447.","apa":"Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., &#38; Ejlali, A. (2008). A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In <i>2008 International Conference on Microelectronics</i> (pp. 444–447). IEEE. <a href=\"https://doi.org/10.1109/ICM.2008.5393497\">https://doi.org/10.1109/ICM.2008.5393497</a>","chicago":"Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” In <i>2008 International Conference on Microelectronics</i>, 444–47. IEEE, 2008. <a href=\"https://doi.org/10.1109/ICM.2008.5393497\">https://doi.org/10.1109/ICM.2008.5393497</a>.","short":"H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–447.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” <i>2008 International Conference on Microelectronics</i>, IEEE, 2008, pp. 444–47, doi:<a href=\"https://doi.org/10.1109/ICM.2008.5393497\">10.1109/ICM.2008.5393497</a>.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}, DOI={<a href=\"https://doi.org/10.1109/ICM.2008.5393497\">10.1109/ICM.2008.5393497</a>}, booktitle={2008 International Conference on Microelectronics}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2008}, pages={444–447} }","ama":"Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In: <i>2008 International Conference on Microelectronics</i>. IEEE; 2008:444-447. doi:<a href=\"https://doi.org/10.1109/ICM.2008.5393497\">10.1109/ICM.2008.5393497</a>"},"publication":"2008 International Conference on Microelectronics"},{"date_updated":"2022-01-06T06:51:40Z","title":"Realizing Reconfigurable Mesh Algorithms on Softcore Arrays","year":"2008","status":"public","author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"user_id":"398","language":[{"iso":"eng"}],"_id":"13629","publisher":"IEEE","publication":"Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)","citation":{"mla":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>, IEEE, 2008.","bibtex":"@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2008} }","ama":"Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In: <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>. IEEE; 2008.","ieee":"H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>, 2008.","apa":"Giefers, H., &#38; Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>. IEEE.","chicago":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” In <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>. IEEE, 2008.","short":"H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008."},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T22:05:22Z"},{"publication":"Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","citation":{"chicago":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” In <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press, 2008.","short":"E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.","ieee":"E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008.","apa":"Lübbers, E., &#38; Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","ama":"Lübbers E, Platzner M. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In: <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008.","mla":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008."},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T22:07:14Z","date_updated":"2022-01-06T06:51:40Z","title":"Communication and Synchronization in Multithreaded Reconfigurable Computing Systems","year":"2008","status":"public","author":[{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"user_id":"398","_id":"13630","publisher":"CSREA Press","language":[{"iso":"eng"}]},{"_id":"13631","publisher":"IEEE","language":[{"iso":"eng"}],"doi":"10.1109/fpl.2008.4629901","user_id":"398","title":"A portable abstraction layer for hardware threads","status":"public","year":"2008","author":[{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_identifier":{"isbn":["9781424419609"]},"date_updated":"2022-01-06T06:51:40Z","publication_status":"published","date_created":"2019-10-04T22:07:43Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)","citation":{"ieee":"E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,” in <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2008.","apa":"Lübbers, E., &#38; Platzner, M. (2008). A portable abstraction layer for hardware threads. In <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE. <a href=\"https://doi.org/10.1109/fpl.2008.4629901\">https://doi.org/10.1109/fpl.2008.4629901</a>","short":"E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.","chicago":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” In <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE, 2008. <a href=\"https://doi.org/10.1109/fpl.2008.4629901\">https://doi.org/10.1109/fpl.2008.4629901</a>.","mla":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2008, doi:<a href=\"https://doi.org/10.1109/fpl.2008.4629901\">10.1109/fpl.2008.4629901</a>.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer for hardware threads}, DOI={<a href=\"https://doi.org/10.1109/fpl.2008.4629901\">10.1109/fpl.2008.4629901</a>}, booktitle={Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","ama":"Lübbers E, Platzner M. A portable abstraction layer for hardware threads. In: <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2008. doi:<a href=\"https://doi.org/10.1109/fpl.2008.4629901\">10.1109/fpl.2008.4629901</a>"}},{"page":"245-251","publisher":"CSREA Press","_id":"2364","language":[{"iso":"eng"}],"user_id":"15278","status":"public","year":"2008","title":"A Hardware Accelerator for k-th Nearest Neighbor Thinning","author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"last_name":"Meiche","first_name":"Robert","full_name":"Meiche, Robert"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"publication_identifier":{"isbn":["1-60132-064-7"]},"date_updated":"2023-09-26T13:54:24Z","date_created":"2018-04-17T11:33:32Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","citation":{"short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","chicago":"Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.","ieee":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008, pp. 245–251.","apa":"Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &#38; Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–251.","bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }","ama":"Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008:245-251.","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008, pp. 245–51."},"quality_controlled":"1"},{"keyword":["IMORC","IP core","interconnect"],"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T12:05:28Z","quality_controlled":"1","publication":"Many-core and Reconfigurable Supercomputing Conference (MRSC)","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>. ; 2008."},"user_id":"15278","language":[{"iso":"eng"}],"_id":"2372","date_updated":"2023-09-26T13:55:51Z","year":"2008","title":"IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers","status":"public","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}]},{"citation":{"apa":"Knieper, T., Defo, B., Kaufmann, P., &#38; Platzner, M. (2008). On Robust Evolution of Digital Hardware. <i>Biologically Inspired Collaborative Computing (BICC)</i>, <i>268</i>, 213–222. <a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">https://doi.org/10.1007/978-0-387-09655-1_19</a>","mla":"Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” <i>Biologically Inspired Collaborative Computing (BICC)</i>, vol. 268, Springer, 2008, pp. 213–22, doi:<a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>.","ieee":"T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of Digital Hardware,” in <i>Biologically Inspired Collaborative Computing (BICC)</i>, 2008, vol. 268, pp. 213–222, doi: <a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>.","short":"T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired Collaborative Computing (BICC), Springer, 2008, pp. 213–222.","ama":"Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital Hardware. In: <i>Biologically Inspired Collaborative Computing (BICC)</i>. Vol 268. IFIP International Federation for Information Processing. Springer; 2008:213-222. doi:<a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>","chicago":"Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On Robust Evolution of Digital Hardware.” In <i>Biologically Inspired Collaborative Computing (BICC)</i>, 268:213–22. IFIP International Federation for Information Processing. Springer, 2008. <a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">https://doi.org/10.1007/978-0-387-09655-1_19</a>.","bibtex":"@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International Federation for Information Processing}, title={On Robust Evolution of Digital Hardware}, volume={268}, DOI={<a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>}, booktitle={Biologically Inspired Collaborative Computing (BICC)}, publisher={Springer}, author={Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={213–222}, collection={IFIP International Federation for Information Processing} }"},"publication":"Biologically Inspired Collaborative Computing (BICC)","date_created":"2019-07-10T11:38:02Z","department":[{"_id":"78"}],"type":"conference","author":[{"last_name":"Knieper","first_name":"Tobias","full_name":"Knieper, Tobias"},{"last_name":"Defo","first_name":"Bertrand","full_name":"Defo, Bertrand"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"title":"On Robust Evolution of Digital Hardware","year":"2008","status":"public","intvolume":"       268","date_updated":"2026-02-19T08:35:12Z","publisher":"Springer","_id":"10698","series_title":"IFIP International Federation for Information Processing","language":[{"iso":"eng"}],"page":"213-222","volume":268,"user_id":"14972","doi":"10.1007/978-0-387-09655-1_19"},{"status":"public","conference":{"end_date":"2007-08-08","start_date":"2007-08-05","name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","location":"Edinburgh, UK"},"page":"447-454","_id":"6508","publisher":"IEEE","user_id":"3118","citation":{"apa":"Kaufmann, P., &#38; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i> (pp. 447–454). Edinburgh, UK: IEEE. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>","ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, Edinburgh, UK, 2007, pp. 447–454.","chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, 447–54. IEEE, 2007. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>.","short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.","mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, IEEE, 2007, pp. 447–54, doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>.","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>. IEEE; 2007:447-454. doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }"},"year":"2007","title":"MOVES: A Modular Framework for Hardware Evolution","author":[{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"publication_identifier":{"isbn":["076952866X","9780769528663"]},"publication_status":"published","date_updated":"2022-01-06T07:03:08Z","language":[{"iso":"eng"}],"doi":"10.1109/ahs.2007.73","publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","abstract":[{"lang":"eng","text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits."}],"date_created":"2019-01-08T09:52:43Z","type":"conference","keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"department":[{"_id":"78"}]},{"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2019-07-10T09:36:57Z","citation":{"bibtex":"@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }","short":"T. Beisel, Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen, Paderborn University, 2007.","ama":"Beisel T. <i>Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen</i>. Paderborn University; 2007.","chicago":"Beisel, Tobias. <i>Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen</i>. Paderborn University, 2007.","ieee":"T. Beisel, <i>Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen</i>. Paderborn University, 2007.","mla":"Beisel, Tobias. <i>Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen</i>. Paderborn University, 2007.","apa":"Beisel, T. (2007). <i>Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen</i>. Paderborn University."},"user_id":"3118","language":[{"iso":"eng"}],"_id":"10623","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:48Z","year":"2007","title":"Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen","status":"public","author":[{"first_name":"Tobias","last_name":"Beisel","full_name":"Beisel, Tobias"}]},{"citation":{"bibtex":"@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={<a href=\"https://doi.org/10.1155/2007/28405\">10.1155/2007/28405</a>}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }","ama":"Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). <i>{EURASIP} Journal on Embedded Systems</i>. 2007;2007:1-2. doi:<a href=\"https://doi.org/10.1155/2007/28405\">10.1155/2007/28405</a>","mla":"Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).” <i>{EURASIP} Journal on Embedded Systems</i>, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:<a href=\"https://doi.org/10.1155/2007/28405\">10.1155/2007/28405</a>.","short":"N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems 2007 (2007) 1–2.","chicago":"Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable Architectures (Editorial).” <i>{EURASIP} Journal on Embedded Systems</i> 2007 (2007): 1–2. <a href=\"https://doi.org/10.1155/2007/28405\">https://doi.org/10.1155/2007/28405</a>.","ieee":"N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” <i>{EURASIP} Journal on Embedded Systems</i>, vol. 2007, pp. 1–2, 2007.","apa":"Bergmann, N., Platzner, M., &#38; Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). <i>{EURASIP} Journal on Embedded Systems</i>, <i>2007</i>, 1–2. <a href=\"https://doi.org/10.1155/2007/28405\">https://doi.org/10.1155/2007/28405</a>"},"publication":"{EURASIP} Journal on Embedded Systems","date_created":"2019-07-10T09:40:11Z","department":[{"_id":"78"}],"type":"journal_article","author":[{"full_name":"Bergmann, Neil","last_name":"Bergmann","first_name":"Neil"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"last_name":"Teich","first_name":"Jürgen","full_name":"Teich, Jürgen"}],"title":"Dynamically Reconfigurable Architectures (editorial)","status":"public","year":"2007","intvolume":"      2007","date_updated":"2022-01-06T06:50:48Z","_id":"10625","publisher":"Springer Science+Business Media","language":[{"iso":"eng"}],"page":"1-2","volume":2007,"user_id":"398","doi":"10.1155/2007/28405"},{"_id":"10643","language":[{"iso":"eng"}],"publisher":"Paderborn University","user_id":"3118","title":"Distributed Simulation of mobile Robots using EyeSim","year":"2007","status":"public","author":[{"first_name":"Toni","last_name":"Ceylan","full_name":"Ceylan, Toni"},{"full_name":"Yalcin, Coni","last_name":"Yalcin","first_name":"Coni"}],"date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:03:44Z","type":"bachelorsthesis","department":[{"_id":"78"}],"supervisor":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"}],"citation":{"mla":"Ceylan, Toni, and Coni Yalcin. <i>Distributed Simulation of Mobile Robots Using EyeSim</i>. Paderborn University, 2007.","bibtex":"@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }","ama":"Ceylan T, Yalcin C. <i>Distributed Simulation of Mobile Robots Using EyeSim</i>. Paderborn University; 2007.","ieee":"T. Ceylan and C. Yalcin, <i>Distributed Simulation of mobile Robots using EyeSim</i>. Paderborn University, 2007.","apa":"Ceylan, T., &#38; Yalcin, C. (2007). <i>Distributed Simulation of mobile Robots using EyeSim</i>. Paderborn University.","short":"T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim, Paderborn University, 2007.","chicago":"Ceylan, Toni, and Coni Yalcin. <i>Distributed Simulation of Mobile Robots Using EyeSim</i>. Paderborn University, 2007."}},{"author":[{"full_name":"Danne, Klaus","last_name":"Danne","first_name":"Klaus"},{"last_name":"Mühlenbernd","first_name":"Roland","full_name":"Mühlenbernd, Roland"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_identifier":{"issn":["1751-8601"]},"title":"Server-based execution of periodic tasks on dynamically reconfigurable hardware","status":"public","year":"2007","intvolume":"         1","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"_id":"10646","page":"295-302","volume":1,"user_id":"3118","doi":"10.1049/iet-cdt:20060186","citation":{"ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” <i>IET Computers Digital Techniques</i>, vol. 1, no. 4, pp. 295–302, 2007.","apa":"Danne, K., Mühlenbernd, R., &#38; Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>, <i>1</i>(4), 295–302. <a href=\"https://doi.org/10.1049/iet-cdt:20060186\">https://doi.org/10.1049/iet-cdt:20060186</a>","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i> 1, no. 4 (2007): 295–302. <a href=\"https://doi.org/10.1049/iet-cdt:20060186\">https://doi.org/10.1049/iet-cdt:20060186</a>.","short":"K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.","mla":"Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i>, vol. 1, no. 4, 2007, pp. 295–302, doi:<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>.","bibtex":"@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }","ama":"Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>. 2007;1(4):295-302. doi:<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>"},"issue":"4","publication":"IET Computers Digital Techniques","date_created":"2019-07-10T11:10:54Z","department":[{"_id":"78"}],"type":"journal_article","keyword":["reconfigurable architectures","resource allocation","device reconfiguration time","dynamic hardware reconfiguration","dynamically reconfigurable hardware","light-weight runtime system","merge server distribute load","periodic real-time tasks","runtime system overheads","schedulability analysis","scheduling technique","server-based execution","synthesis tool flow"]},{"date_created":"2019-07-10T11:10:55Z","type":"mastersthesis","department":[{"_id":"78"}],"citation":{"apa":"Defo, B. (2007). <i>A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization</i>. Paderborn University.","ieee":"B. Defo, <i>A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization</i>. Paderborn University, 2007.","short":"B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization, Paderborn University, 2007.","chicago":"Defo, Bertrand. <i>A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization</i>. Paderborn University, 2007.","mla":"Defo, Bertrand. <i>A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization</i>. Paderborn University, 2007.","ama":"Defo B. <i>A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization</i>. Paderborn University; 2007.","bibtex":"@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }"},"supervisor":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"}],"_id":"10647","publisher":"Paderborn University","language":[{"iso":"eng"}],"user_id":"3118","status":"public","year":"2007","title":"A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization","author":[{"last_name":"Defo","first_name":"Bertrand","full_name":"Defo, Bertrand"}],"date_updated":"2022-01-06T06:50:49Z"}]