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The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. "}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","citation":{"bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>}, booktitle={Proc. Int. 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Paderborn University; 2006.","bibtex":"@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }","apa":"Mühlenbernd, R. (2006). <i>FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks</i>. Paderborn University.","ieee":"R. Mühlenbernd, <i>FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks</i>. Paderborn University, 2006.","short":"R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006.","chicago":"Mühlenbernd, Roland. <i>FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks</i>. Paderborn University, 2006."},"department":[{"_id":"78"}],"type":"bachelorsthesis","date_created":"2019-07-10T11:48:27Z","date_updated":"2022-01-06T06:50:50Z","author":[{"first_name":"Roland","last_name":"Mühlenbernd","full_name":"Mühlenbernd, Roland"}],"title":"FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks","year":"2006","status":"public","user_id":"3118","_id":"10716","publisher":"Paderborn University","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:51:40Z","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"first_name":"Roland","last_name":"Mühlenbernd","full_name":"Mühlenbernd, Roland"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"status":"public","year":"2006","title":"Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions","user_id":"398","_id":"13624","language":[{"iso":"eng"}],"publisher":"IEEE","citation":{"bibtex":"@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }","ama":"Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: <i>Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2006.","mla":"Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” <i>Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2006.","short":"K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” In <i>Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE, 2006.","ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in <i>Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2006.","apa":"Danne, K., Mühlenbernd, R., &#38; Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In <i>Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE."},"publication":"Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"type":"conference","date_created":"2019-10-04T21:48:42Z"},{"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T21:51:29Z","publication":"In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)","citation":{"short":"K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.","chicago":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In <i>In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)</i>, 2006.","ieee":"K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in <i>In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)</i>, 2006.","apa":"Danne, K., &#38; Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In <i>In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)</i>.","bibtex":"@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","ama":"Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: <i>In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)</i>. ; 2006.","mla":"Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” <i>In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)</i>, 2006."},"user_id":"398","_id":"13625","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:40Z","status":"public","year":"2006","title":"An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices","author":[{"first_name":"Klaus","last_name":"Danne","full_name":"Danne, Klaus"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}]},{"citation":{"bibtex":"@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }","ama":"Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: <i>Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)</i>. IEEE CS Press; 2006.","mla":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” <i>Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)</i>, IEEE CS Press, 2006.","short":"K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.","chicago":"Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In <i>Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)</i>. IEEE CS Press, 2006.","ieee":"K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in <i>Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)</i>, 2006.","apa":"Danne, K., &#38; Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In <i>Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)</i>. IEEE CS Press."},"publication":"Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"78"}],"type":"conference","date_created":"2019-10-04T21:53:12Z","date_updated":"2022-01-06T06:51:40Z","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"status":"public","year":"2006","title":"Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware","user_id":"398","_id":"13626","publisher":"IEEE CS Press","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:56:07Z","title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","status":"public","year":"2005","author":[{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"doi":"10.1109/ASAP.2005.69","user_id":"24135","page":"213-218","_id":"2411","publisher":"IEEE Computer Society","abstract":[{"text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. ","lang":"eng"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","citation":{"mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2005, pp. 213–18, doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2005:213-218. doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2005, pp. 213–218.","apa":"Plessl, C., &#38; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i> (pp. 213–218). IEEE Computer Society. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>","chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 213–18. IEEE Computer Society, 2005. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218."},"keyword":["Zippy"],"type":"conference","department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T14:34:03Z"},{"date_updated":"2022-01-06T06:56:07Z","intvolume":"        29","year":"2005","title":"System-level performance evaluation of reconfigurable processors","status":"public","author":[{"full_name":"Enzler, Rolf","last_name":"Enzler","first_name":"Rolf"},{"id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"doi":"10.1016/j.micpro.2004.06.004","user_id":"24135","volume":29,"page":"63-73","_id":"2412","publisher":"Elsevier","abstract":[{"text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.","lang":"eng"}],"issue":"2-3","publication":"Microprocessors and Microsystems","citation":{"bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>. 2005;29(2-3):63-73. doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i> 29, no. 2–3 (2005): 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>.","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, pp. 63–73, 2005.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>, <i>29</i>(2–3), 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>"},"keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"type":"journal_article","department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T14:36:10Z"},{"_id":"13621","language":[{"iso":"eng"}],"user_id":"398","doi":"10.1109/wises.2005.1438720","year":"2005","status":"public","title":"Periodic real-time scheduling for FPGA computers","publication_identifier":{"isbn":["3902463031"]},"author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_status":"published","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T21:38:53Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)","citation":{"apa":"Danne, K., &#38; Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In <i>Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)</i>. <a href=\"https://doi.org/10.1109/wises.2005.1438720\">https://doi.org/10.1109/wises.2005.1438720</a>","ieee":"K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in <i>Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)</i>, 2005.","chicago":"Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” In <i>Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)</i>, 2005. <a href=\"https://doi.org/10.1109/wises.2005.1438720\">https://doi.org/10.1109/wises.2005.1438720</a>.","short":"K. Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.","mla":"Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” <i>Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)</i>, 2005, doi:<a href=\"https://doi.org/10.1109/wises.2005.1438720\">10.1109/wises.2005.1438720</a>.","ama":"Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. In: <i>Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)</i>. ; 2005. doi:<a href=\"https://doi.org/10.1109/wises.2005.1438720\">10.1109/wises.2005.1438720</a>","bibtex":"@inproceedings{Danne_Platzner_2005, title={Periodic real-time scheduling for FPGA computers}, DOI={<a href=\"https://doi.org/10.1109/wises.2005.1438720\">10.1109/wises.2005.1438720</a>}, booktitle={Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }"}},{"date_created":"2019-10-04T21:42:02Z","department":[{"_id":"78"}],"type":"conference","citation":{"ieee":"K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in <i>Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)</i>, 2005.","apa":"Danne, K., &#38; Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In <i>Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)</i>.","chicago":"Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” In <i>Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS)</i>, 2005.","short":"K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.","mla":"Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” <i>Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS)</i>, 2005.","bibtex":"@inproceedings{Danne_Platzner_2005, title={Memory-demanding Periodic Real-time Applications on FPGA Computers}, booktitle={Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }","ama":"Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: <i>Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS)</i>. ; 2005."},"publication":"Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)","_id":"13622","language":[{"iso":"eng"}],"user_id":"398","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"status":"public","year":"2005","title":"Memory-demanding Periodic Real-time Applications on FPGA Computers","date_updated":"2022-01-06T06:51:40Z"},{"doi":"10.1109/fpl.2005.1515787","user_id":"398","_id":"13623","publisher":"IEEE CS Press","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:40Z","publication_status":"published","title":"A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware","year":"2005","status":"public","author":[{"last_name":"Danne","first_name":"Klaus","full_name":"Danne, Klaus"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"publication_identifier":{"isbn":["0780393627"]},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T21:42:46Z","publication":"Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)","citation":{"chicago":"Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” In <i>Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE CS Press, 2005. <a href=\"https://doi.org/10.1109/fpl.2005.1515787\">https://doi.org/10.1109/fpl.2005.1515787</a>.","ama":"Danne K, Platzner M. A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In: <i>Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE CS Press; 2005. doi:<a href=\"https://doi.org/10.1109/fpl.2005.1515787\">10.1109/fpl.2005.1515787</a>","short":"K. Danne, M. Platzner, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005.","bibtex":"@inproceedings{Danne_Platzner_2005, title={A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}, DOI={<a href=\"https://doi.org/10.1109/fpl.2005.1515787\">10.1109/fpl.2005.1515787</a>}, booktitle={Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2005} }","apa":"Danne, K., &#38; Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In <i>Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE CS Press. <a href=\"https://doi.org/10.1109/fpl.2005.1515787\">https://doi.org/10.1109/fpl.2005.1515787</a>","mla":"Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” <i>Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE CS Press, 2005, doi:<a href=\"https://doi.org/10.1109/fpl.2005.1515787\">10.1109/fpl.2005.1515787</a>.","ieee":"K. Danne and M. Platzner, “A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware,” in <i>Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2005."}},{"abstract":[{"lang":"eng","text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. "}],"citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 63–69. CSREA Press, 2004.","apa":"Plessl, C., &#38; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 63–69). CSREA Press.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2004, pp. 63–69.","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2004:63-69.","bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2004, pp. 63–69."},"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["hardware virtualization"],"date_created":"2018-04-17T14:45:57Z","date_updated":"2022-01-06T06:56:08Z","author":[{"id":"16153","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"Virtualization of Hardware – Introduction and Survey","year":"2004","status":"public","user_id":"24135","publisher":"CSREA Press","_id":"2415","page":"63-69"}]