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Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion,” in <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Boston, MA, USA, 2022, pp. 2071–2079, doi: <a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>.","apa":"Hansmeier, T., Brede, M., &#38; Platzner, M. (2022). XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 2071–2079. <a href=\"https://doi.org/10.1145/3520304.3533977\">https://doi.org/10.1145/3520304.3533977</a>","chicago":"Hansmeier, Tim, Mathis Brede, and Marco Platzner. “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion.” In <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 2071–79. New York, NY, United States: Association for Computing Machinery (ACM), 2022. <a href=\"https://doi.org/10.1145/3520304.3533977\">https://doi.org/10.1145/3520304.3533977</a>.","short":"T. Hansmeier, M. Brede, M. Platzner, in: GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2022, pp. 2071–2079.","mla":"Hansmeier, Tim, et al. “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion.” <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Association for Computing Machinery (ACM), 2022, pp. 2071–79, doi:<a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>.","bibtex":"@inproceedings{Hansmeier_Brede_Platzner_2022, place={New York, NY, United States}, title={XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}, DOI={<a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>}, booktitle={GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Brede, Mathis and Platzner, Marco}, year={2022}, pages={2071–2079} }","ama":"Hansmeier T, Brede M, Platzner M. XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. In: <i>GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>. Association for Computing Machinery (ACM); 2022:2071-2079. doi:<a href=\"https://doi.org/10.1145/3520304.3533977\">10.1145/3520304.3533977</a>"},"project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"}],"place":"New York, NY, United States","date_created":"2022-09-02T11:47:17Z","type":"conference","department":[{"_id":"78"}]},{"has_accepted_license":"1","status":"public","ddc":["004"],"user_id":"477","publisher":" Paderborn University, Paderborn, Germany","_id":"29769","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"name":"SFB 901 - C2: SFB 901 - Subproject C2","_id":"14"}],"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"citation":{"apa":"Ahmed, Q. A. (2022). <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany. <a href=\"https://doi.org/10.17619/UNIPB/1-1271\">https://doi.org/10.17619/UNIPB/1-1271</a>","ieee":"Q. A. Ahmed, <i>Hardware Trojans in Reconfigurable Computing</i>. Paderborn:  Paderborn University, Paderborn, Germany, 2022.","chicago":"Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>. Paderborn:  Paderborn University, Paderborn, Germany, 2022. <a href=\"https://doi.org/10.17619/UNIPB/1-1271\">https://doi.org/10.17619/UNIPB/1-1271</a>.","short":"Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing,  Paderborn University, Paderborn, Germany, Paderborn, 2022.","mla":"Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany, 2022, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>.","ama":"Ahmed QA. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany; 2022. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>","bibtex":"@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>}, publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab}, year={2022} }"},"oa":"1","place":"Paderborn","date_updated":"2022-11-30T13:39:01Z","publication_status":"published","year":"2022","title":"Hardware Trojans in Reconfigurable Computing","author":[{"id":"72764","full_name":"Ahmed, Qazi Arbab","orcid":"0000-0002-1837-2254","last_name":"Ahmed","first_name":"Qazi Arbab"}],"doi":"10.17619/UNIPB/1-1271","main_file_link":[{"url":"\turn:nbn:de:hbz:466:2-40303","open_access":"1"}],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden."},{"lang":"eng","text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable systems, the defenders perspective which corresponds to the bitstream-level Trojan detection technique, and the attackers perspective which corresponds to a novel FPGA Trojan attack. From the defender's perspective, we introduce a first-ever successful pre-configuration countermeasure against the ``Malicious LUT''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers perspective, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by bitstream-level verification techniques."}],"keyword":["FPGA Security","Hardware Trojans","Bitstream-level Trojans","Bitstream Verification"],"type":"dissertation","department":[{"_id":"78"}],"date_created":"2022-02-07T14:02:36Z"},{"status":"public","year":"2022","title":"ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications","author":[{"id":"60323","full_name":"Lienen, Christian","first_name":"Christian","last_name":"Lienen"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"date_updated":"2022-01-28T08:30:16Z","main_file_link":[{"url":"https://arxiv.org/abs/2201.07454"}],"_id":"29541","language":[{"iso":"eng"}],"user_id":"60323","citation":{"mla":"Lienen, Christian, and Marco Platzner. <i>ReconROS Executor: Event-Driven Programming of FPGA-Accelerated ROS 2 Applications</i>. 2022.","ama":"Lienen C, Platzner M. ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications. Published online 2022.","bibtex":"@article{Lienen_Platzner_2022, title={ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications}, author={Lienen, Christian and Platzner, Marco}, year={2022} }","apa":"Lienen, C., &#38; Platzner, M. (2022). <i>ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications</i>.","ieee":"C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.” 2022.","short":"C. Lienen, M. Platzner, (2022).","chicago":"Lienen, Christian, and Marco Platzner. “ReconROS Executor: Event-Driven Programming of FPGA-Accelerated ROS 2 Applications,” 2022."},"date_created":"2022-01-26T08:52:20Z","type":"preprint","department":[{"_id":"78"}]},{"citation":{"ieee":"C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.","apa":"Lienen, C., &#38; Platzner, M. (n.d.). <i>Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS</i>. 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.","short":"C. Lienen, M. Platzner, in: n.d.","chicago":"Lienen, Christian, and Marco Platzner. “Task Mapping for Hardware-Accelerated Robotics Applications Using ReconROS,” n.d.","mla":"Lienen, Christian, and Marco Platzner. <i>Task Mapping for Hardware-Accelerated Robotics Applications Using ReconROS</i>.","bibtex":"@inproceedings{Lienen_Platzner, title={Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS}, author={Lienen, Christian and Platzner, Marco} }","ama":"Lienen C, Platzner M. Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS."},"type":"conference","department":[{"_id":"78"}],"date_created":"2022-11-04T09:26:42Z","date_updated":"2022-11-04T09:26:47Z","publication_status":"accepted","year":"2022","title":"Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS","status":"public","conference":{"location":"Neaples, Italy","name":"2022 Sixth IEEE International Conference on Robotic Computing (IRC) "},"author":[{"full_name":"Lienen, Christian","last_name":"Lienen","first_name":"Christian","id":"60323"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"60323","language":[{"iso":"eng"}],"_id":"34007"},{"publication_status":"accepted","date_updated":"2023-01-06T06:38:27Z","status":"public","title":"Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications","year":"2022","author":[{"full_name":"Lienen, Christian","last_name":"Lienen","first_name":"Christian","id":"60323"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"conference":{"location":"Maspalomas, Gran Canaria, Spain","name":"25th Euromicro Conference on Digital System Design (DSD)"},"user_id":"60323","doi":"10.1109/DSD57027.2022.00088","_id":"34005","language":[{"iso":"eng"}],"publication":"2022 25th Euromicro Conference on Digital System Design (DSD)","citation":{"apa":"Lienen, C., &#38; Platzner, M. (n.d.). Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>. 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain. <a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">https://doi.org/10.1109/DSD57027.2022.00088</a>","ieee":"C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,” presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi: <a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>.","chicago":"Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated ROS 2 Robotics Applications.” In <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>, n.d. <a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">https://doi.org/10.1109/DSD57027.2022.00088</a>.","short":"C. Lienen, M. Platzner, in: 2022 25th Euromicro Conference on Digital System Design (DSD), n.d.","mla":"Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated ROS 2 Robotics Applications.” <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>, doi:<a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>.","ama":"Lienen C, Platzner M. Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. In: <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>. doi:<a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>","bibtex":"@inproceedings{Lienen_Platzner, title={Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications}, DOI={<a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>}, booktitle={2022 25th Euromicro Conference on Digital System Design (DSD)}, author={Lienen, Christian and Platzner, Marco} }"},"type":"conference","department":[{"_id":"78"}],"date_created":"2022-11-04T09:24:47Z"},{"department":[{"_id":"78"}],"type":"dissertation","date_created":"2022-11-09T06:26:22Z","project":[{"name":"SFB 901: SFB 901","_id":"1"},{"name":"SFB 901 - B: SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901 - B4: SFB 901 - Subproject B4","_id":"12"}],"supervisor":[{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"citation":{"bibtex":"@book{Witschen_2022, title={Frameworks and Methodologies for Search-based Approximate Logic Synthesis}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1649\">10.17619/UNIPB/1-1649</a>}, author={Witschen, Linus Matthias}, year={2022} }","ama":"Witschen LM. <i>Frameworks and Methodologies for Search-Based Approximate Logic Synthesis</i>.; 2022. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1649\">10.17619/UNIPB/1-1649</a>","mla":"Witschen, Linus Matthias. <i>Frameworks and Methodologies for Search-Based Approximate Logic Synthesis</i>. 2022, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1649\">10.17619/UNIPB/1-1649</a>.","chicago":"Witschen, Linus Matthias. <i>Frameworks and Methodologies for Search-Based Approximate Logic Synthesis</i>, 2022. <a href=\"https://doi.org/10.17619/UNIPB/1-1649\">https://doi.org/10.17619/UNIPB/1-1649</a>.","short":"L.M. Witschen, Frameworks and Methodologies for Search-Based Approximate Logic Synthesis, 2022.","ieee":"L. M. Witschen, <i>Frameworks and Methodologies for Search-based Approximate Logic Synthesis</i>. 2022.","apa":"Witschen, L. M. (2022). <i>Frameworks and Methodologies for Search-based Approximate Logic Synthesis</i>. <a href=\"https://doi.org/10.17619/UNIPB/1-1649\">https://doi.org/10.17619/UNIPB/1-1649</a>"},"doi":"10.17619/UNIPB/1-1649","user_id":"15504","language":[{"iso":"eng"}],"_id":"34041","date_updated":"2023-01-19T06:41:22Z","author":[{"full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","last_name":"Witschen","id":"49051"}],"status":"public","title":"Frameworks and Methodologies for Search-based Approximate Logic Synthesis","year":"2022"},{"_id":"32342","publisher":"IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)","language":[{"iso":"eng"}],"user_id":"72764","author":[{"id":"72764","full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed","orcid":"0000-0002-1837-2254","first_name":"Qazi Arbab"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"conference":{"start_date":" July 4, 2022","name":"IEEE Computer Society Annual Symposium on VLSI Aliathon Resort,","location":"Pafos, Cyprus","end_date":"July 6, 2022"},"title":"On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs","year":"2022","status":"public","date_updated":"2023-04-19T15:04:30Z","date_created":"2022-07-12T19:56:48Z","place":"Pafos, Cyprus","department":[{"_id":"78"}],"type":"conference","citation":{"mla":"Ahmed, Qazi Arbab, and Marco Platzner. <i>On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs</i>. IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), 2022.","bibtex":"@inproceedings{Ahmed_Platzner_2022, place={Pafos, Cyprus}, title={On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs}, publisher={IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)}, author={Ahmed, Qazi Arbab and Platzner, Marco}, year={2022} }","ama":"Ahmed QA, Platzner M. On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022); 2022.","ieee":"Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus, 2022.","apa":"Ahmed, Q. A., &#38; Platzner, M. (2022). <i>On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs</i>. IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus.","short":"Q.A. Ahmed, M. Platzner, in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), Pafos, Cyprus, 2022.","chicago":"Ahmed, Qazi Arbab, and Marco Platzner. “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs.” Pafos, Cyprus: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), 2022."},"project":[{"_id":"1","name":"SFB 901: SFB 901"},{"name":"SFB 901 - B: SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"}]},{"date_created":"2022-11-03T14:42:16Z","department":[{"_id":"78"}],"type":"journal_article","publication":"IEEE Micro","issue":"6","abstract":[{"lang":"eng","text":"Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes."}],"language":[{"iso":"eng"}],"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9933377"}],"doi":"10.1109/MM.2022.3202091","author":[{"full_name":"Jentzsch, Felix","first_name":"Felix","orcid":"0000-0003-4987-5708","last_name":"Jentzsch","id":"55631"},{"first_name":"Yaman","last_name":"Umuroglu","full_name":"Umuroglu, Yaman"},{"full_name":"Pappalardo, Alessandro","first_name":"Alessandro","last_name":"Pappalardo"},{"full_name":"Blott, Michaela","last_name":"Blott","first_name":"Michaela"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"title":"RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures","year":"2022","intvolume":"        42","publication_status":"published","date_updated":"2023-04-04T15:09:17Z","citation":{"short":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro 42 (2022) 125–133.","chicago":"Jentzsch, Felix, Yaman Umuroglu, Alessandro Pappalardo, Michaela Blott, and Marco Platzner. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” <i>IEEE Micro</i> 42, no. 6 (2022): 125–33. <a href=\"https://doi.org/10.1109/MM.2022.3202091\">https://doi.org/10.1109/MM.2022.3202091</a>.","apa":"Jentzsch, F., Umuroglu, Y., Pappalardo, A., Blott, M., &#38; Platzner, M. (2022). RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. <i>IEEE Micro</i>, <i>42</i>(6), 125–133. <a href=\"https://doi.org/10.1109/MM.2022.3202091\">https://doi.org/10.1109/MM.2022.3202091</a>","ieee":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,” <i>IEEE Micro</i>, vol. 42, no. 6, pp. 125–133, 2022, doi: <a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>.","ama":"Jentzsch F, Umuroglu Y, Pappalardo A, Blott M, Platzner M. RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. <i>IEEE Micro</i>. 2022;42(6):125-133. doi:<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>","bibtex":"@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}, volume={42}, DOI={<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>}, number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}, year={2022}, pages={125–133} }","mla":"Jentzsch, Felix, et al. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” <i>IEEE Micro</i>, vol. 42, no. 6, IEEE, 2022, pp. 125–33, doi:<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>."},"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"33990","publisher":"IEEE","page":"125-133","volume":42,"user_id":"55631","status":"public"},{"supervisor":[{"first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","id":"74287"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209"}],"citation":{"short":"V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators, 2022.","chicago":"Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>, 2022.","apa":"Tcheussi Ngayap, V. I. (2022). <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>.","ieee":"V. I. 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