[{"doi":"10.1109/ipdps.2003.1213329","user_id":"398","_id":"13613","language":[{"iso":"eng"}],"publisher":"IEEE CS Press","date_updated":"2022-01-06T06:51:40Z","publication_status":"published","year":"2003","title":"Fast online task placement on FPGAs: free space partitioning and 2D-hashing","status":"public","publication_identifier":{"isbn":["0769519261"]},"author":[{"full_name":"Walder, Herbert","last_name":"Walder","first_name":"Herbert"},{"full_name":"Steiger, Christoph","first_name":"Christoph","last_name":"Steiger"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T21:17:07Z","extern":"1","publication":"Proceedings International Parallel and Distributed Processing Symposium","citation":{"apa":"Walder, H., Steiger, C., &#38; Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In <i>Proceedings International Parallel and Distributed Processing Symposium</i>. IEEE CS Press. <a href=\"https://doi.org/10.1109/ipdps.2003.1213329\">https://doi.org/10.1109/ipdps.2003.1213329</a>","ieee":"H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in <i>Proceedings International Parallel and Distributed Processing Symposium</i>, 2003.","chicago":"Walder, Herbert, Christoph Steiger, and Marco Platzner. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” In <i>Proceedings International Parallel and Distributed Processing Symposium</i>. IEEE CS Press, 2003. <a href=\"https://doi.org/10.1109/ipdps.2003.1213329\">https://doi.org/10.1109/ipdps.2003.1213329</a>.","short":"H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.","mla":"Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” <i>Proceedings International Parallel and Distributed Processing Symposium</i>, IEEE CS Press, 2003, doi:<a href=\"https://doi.org/10.1109/ipdps.2003.1213329\">10.1109/ipdps.2003.1213329</a>.","ama":"Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: <i>Proceedings International Parallel and Distributed Processing Symposium</i>. IEEE CS Press; 2003. doi:<a href=\"https://doi.org/10.1109/ipdps.2003.1213329\">10.1109/ipdps.2003.1213329</a>","bibtex":"@inproceedings{Walder_Steiger_Platzner_2003, title={Fast online task placement on FPGAs: free space partitioning and 2D-hashing}, DOI={<a href=\"https://doi.org/10.1109/ipdps.2003.1213329\">10.1109/ipdps.2003.1213329</a>}, booktitle={Proceedings International Parallel and Distributed Processing Symposium}, publisher={IEEE CS Press}, author={Walder, Herbert and Steiger, Christoph and Platzner, Marco}, year={2003} }"}},{"date_created":"2019-10-04T21:20:30Z","department":[{"_id":"78"}],"type":"conference","citation":{"short":"H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287.","ama":"Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: <i>Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2003:284-287.","chicago":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” In <i>Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 284–87. CSREA Press, 2003.","bibtex":"@inproceedings{Walder_Platzner_2003, title={Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}, booktitle={Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={284–287} }","mla":"Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” <i>Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2003, pp. 284–87.","apa":"Walder, H., &#38; Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In <i>Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 284–287). CSREA Press.","ieee":"H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in <i>Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2003, pp. 284–287."},"publication":"Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","extern":"1","_id":"13614","language":[{"iso":"eng"}],"publisher":"CSREA Press","page":"284-287","user_id":"398","author":[{"first_name":"Herbert","last_name":"Walder","full_name":"Walder, Herbert"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"status":"public","title":"Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations","year":"2003","date_updated":"2022-01-06T06:51:40Z"},{"publication_status":"published","date_updated":"2022-01-06T06:51:40Z","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540408222","9783540452348"]},"author":[{"last_name":"Steiger","first_name":"Christoph","full_name":"Steiger, Christoph"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"status":"public","title":"Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices","year":"2003","user_id":"398","doi":"10.1007/978-3-540-45234-8_56","publisher":"Springer","_id":"13615","language":[{"iso":"eng"}],"page":"575-584","extern":"1","citation":{"mla":"Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” <i>Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)</i>, Springer, 2003, pp. 575–84, doi:<a href=\"https://doi.org/10.1007/978-3-540-45234-8_56\">10.1007/978-3-540-45234-8_56</a>.","bibtex":"@inproceedings{Steiger_Walder_Platzner_2003, place={Berlin, Heidelberg}, title={Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}, DOI={<a href=\"https://doi.org/10.1007/978-3-540-45234-8_56\">10.1007/978-3-540-45234-8_56</a>}, booktitle={Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2003}, pages={575–584} }","ama":"Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: <i>Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)</i>. Berlin, Heidelberg: Springer; 2003:575-584. doi:<a href=\"https://doi.org/10.1007/978-3-540-45234-8_56\">10.1007/978-3-540-45234-8_56</a>","ieee":"C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in <i>Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2003, pp. 575–584.","apa":"Steiger, C., Walder, H., &#38; Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In <i>Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)</i> (pp. 575–584). Berlin, Heidelberg: Springer. <a href=\"https://doi.org/10.1007/978-3-540-45234-8_56\">https://doi.org/10.1007/978-3-540-45234-8_56</a>","short":"C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584.","chicago":"Steiger, Christoph, Herbert Walder, and Marco Platzner. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” In <i>Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)</i>, 575–84. Berlin, Heidelberg: Springer, 2003. <a href=\"https://doi.org/10.1007/978-3-540-45234-8_56\">https://doi.org/10.1007/978-3-540-45234-8_56</a>."},"publication":"Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"type":"conference","date_created":"2019-10-04T21:20:41Z","place":"Berlin, Heidelberg"},{"language":[{"iso":"eng"}],"_id":"13617","publisher":"IEEE CS Press","page":"224-225","doi":"10.1109/real.2003.1253269","user_id":"14972","author":[{"full_name":"Steiger, Christoph","first_name":"Christoph","last_name":"Steiger"},{"first_name":"Herbert","last_name":"Walder","full_name":"Walder, Herbert"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"publication_identifier":{"isbn":["0769520448"]},"year":"2003","title":"Online scheduling and placement of real-time tasks to partially reconfigurable devices","status":"public","date_updated":"2026-02-23T16:04:54Z","publication_status":"published","date_created":"2019-10-04T21:22:53Z","department":[{"_id":"78"}],"type":"conference","citation":{"ieee":"C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in <i>Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)</i>, 2003, pp. 224–225, doi: <a href=\"https://doi.org/10.1109/real.2003.1253269\">10.1109/real.2003.1253269</a>.","apa":"Steiger, C., Walder, H., Platzner, M., &#38; Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. <i>Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)</i>, 224–225. <a href=\"https://doi.org/10.1109/real.2003.1253269\">https://doi.org/10.1109/real.2003.1253269</a>","mla":"Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” <i>Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)</i>, IEEE CS Press, 2003, pp. 224–25, doi:<a href=\"https://doi.org/10.1109/real.2003.1253269\">10.1109/real.2003.1253269</a>.","bibtex":"@inproceedings{Steiger_Walder_Platzner_Thiele_2003, title={Online scheduling and placement of real-time tasks to partially reconfigurable devices}, DOI={<a href=\"https://doi.org/10.1109/real.2003.1253269\">10.1109/real.2003.1253269</a>}, booktitle={Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}, publisher={IEEE CS Press}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}, year={2003}, pages={224–225} }","chicago":"Steiger, Christoph, Herbert Walder, Marco Platzner, and Lothar Thiele. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” In <i>Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)</i>, 224–25. IEEE CS Press, 2003. <a href=\"https://doi.org/10.1109/real.2003.1253269\">https://doi.org/10.1109/real.2003.1253269</a>.","short":"C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 224–225.","ama":"Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: <i>Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)</i>. IEEE CS Press; 2003:224-225. doi:<a href=\"https://doi.org/10.1109/real.2003.1253269\">10.1109/real.2003.1253269</a>"},"publication":"Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)"},{"abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM."}],"publication":"Proc. Int. Symp. on Wearable Computers (ISWC)","citation":{"mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, IEEE Computer Society, 2002, pp. 215–22, doi:<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>.","ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>. IEEE Computer Society; 2002:215-222. doi:<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>","bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &#38; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i> (pp. 215–222). IEEE Computer Society. <a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">https://doi.org/10.1109/ISWC.2002.1167250</a>","ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, 2002, pp. 215–222.","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, 215–22. IEEE Computer Society, 2002. <a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">https://doi.org/10.1109/ISWC.2002.1167250</a>.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222."},"keyword":["wearable computing"],"type":"conference","department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:13:50Z","date_updated":"2022-01-06T06:56:13Z","title":"Reconfigurable Hardware in Wearable Computing Nodes","year":"2002","status":"public","publication_identifier":{"isbn":["0-7695-1816-8"]},"author":[{"full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Enzler, Rolf","last_name":"Enzler","first_name":"Rolf"},{"first_name":"Herbert","last_name":"Walder","full_name":"Walder, Herbert"},{"full_name":"Beutel, Jan","last_name":"Beutel","first_name":"Jan"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"user_id":"24135","doi":"10.1109/ISWC.2002.1167250","page":"215-222","publisher":"IEEE Computer Society","_id":"2423"},{"date_updated":"2022-01-06T06:56:13Z","intvolume":"      2438","year":"2002","status":"public","title":"Partially Reconfigurable Cores for Xilinx Virtex","author":[{"last_name":"Dyer","first_name":"Matthias","full_name":"Dyer, Matthias"},{"id":"16153","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"doi":"10.1007/3-540-46117-5","user_id":"24135","volume":2438,"page":"292-301","_id":"2424","publisher":"Springer","series_title":"Lecture Notes in Computer Science (LNCS)","abstract":[{"lang":"eng","text":" Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. "}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","citation":{"ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2002, vol. 2438, pp. 292–301.","apa":"Dyer, M., Plessl, C., &#38; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i> (Vol. 2438, pp. 292–301). Springer. <a href=\"https://doi.org/10.1007/3-540-46117-5\">https://doi.org/10.1007/3-540-46117-5</a>","chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. <a href=\"https://doi.org/10.1007/3-540-46117-5\">https://doi.org/10.1007/3-540-46117-5</a>.","short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, vol. 2438, Springer, 2002, pp. 292–301, doi:<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>.","bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>"},"type":"conference","keyword":["partial reconfiguration"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:14:39Z"},{"page":"163-172","publisher":"IEEE Computer Society","_id":"2425","user_id":"24135","doi":"10.1109/FPGA.2002.1106671","title":"Custom Computing Machines for the Set Covering Problem","year":"2002","status":"public","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-01-06T06:56:13Z","date_created":"2018-04-17T15:15:44Z","type":"conference","department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","citation":{"mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2002, pp. 163–72, doi:<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>.","bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2002:163-172. doi:<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>","ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2002, pp. 163–172.","apa":"Plessl, C., &#38; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i> (pp. 163–172). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">https://doi.org/10.1109/FPGA.2002.1106671</a>","short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.","chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 163–72. IEEE Computer Society, 2002. <a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">https://doi.org/10.1109/FPGA.2002.1106671</a>."},"abstract":[{"text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. ","lang":"eng"}]},{"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T11:13:11Z","extern":"1","publication":"The Journal of Supercomputing","issue":"2","citation":{"short":"M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159.","chicago":"Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” <i>The Journal of Supercomputing</i> 21, no. 2 (2002): 145–59. <a href=\"https://doi.org/10.1023/a:1013627403946\">https://doi.org/10.1023/a:1013627403946</a>.","ieee":"M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” <i>The Journal of Supercomputing</i>, vol. 21, no. 2, pp. 145–159, 2002.","apa":"Eisenring, M., &#38; Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. <i>The Journal of Supercomputing</i>, <i>21</i>(2), 145–159. <a href=\"https://doi.org/10.1023/a:1013627403946\">https://doi.org/10.1023/a:1013627403946</a>","bibtex":"@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable Systems}, volume={21}, DOI={<a href=\"https://doi.org/10.1023/a:1013627403946\">10.1023/a:1013627403946</a>}, number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159} }","ama":"Eisenring M, Platzner M. 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(2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In <i>Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 24–30). CSREA Press.","ieee":"H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in <i>Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2002, pp. 24–30.","chicago":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” In <i>Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 24–30. CSREA Press, 2002.","short":"H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.","mla":"Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” <i>Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2002, pp. 24–30.","ama":"Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: <i>Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2002:24-30.","bibtex":"@inproceedings{Walder_Platzner_2002, title={Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}, booktitle={Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2002}, pages={24–30} }"},"publication":"Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)"},{"date_updated":"2022-01-06T06:56:17Z","status":"public","title":"Instance-Specific Accelerators for Minimum Covering","year":"2001","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"user_id":"24135","page":"85-91","publisher":"CSREA Press","_id":"2428","abstract":[{"text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. ","lang":"eng"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","citation":{"bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2001:85-91.","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2001, pp. 85–91.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 85–91. CSREA Press, 2001.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2001, pp. 85–91.","apa":"Plessl, C., &#38; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 85–91). CSREA Press."},"type":"conference","keyword":["minimum covering","accelerator","funding-sundance"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:39:17Z"},{"page":"135-146","series_title":"Proc. SPIE","_id":"2432","user_id":"24135","doi":"10.1117/12.434376","volume":4525,"year":"2001","status":"public","title":"Reconfigurable Processors for Handhelds and Wearables: Application Analysis","author":[{"first_name":"Rolf","last_name":"Enzler","full_name":"Enzler, Rolf"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"},{"full_name":"Tröster, Gerhard","first_name":"Gerhard","last_name":"Tröster"}],"date_updated":"2022-01-06T06:56:17Z","intvolume":"      4525","date_created":"2018-04-17T15:51:39Z","keyword":["benchmark"],"type":"conference","department":[{"_id":"518"},{"_id":"78"}],"publication":"Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III","citation":{"ieee":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, 2001, vol. 4525, pp. 135–146.","apa":"Enzler, R., Platzner, M., Plessl, C., Thiele, L., &#38; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i> (Vol. 4525, pp. 135–146). <a href=\"https://doi.org/10.1117/12.434376\">https://doi.org/10.1117/12.434376</a>","short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.","chicago":"Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, 4525:135–46. Proc. SPIE, 2001. <a href=\"https://doi.org/10.1117/12.434376\">https://doi.org/10.1117/12.434376</a>.","mla":"Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, vol. 4525, 2001, pp. 135–46, doi:<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>.","bibtex":"@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }","ama":"Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>"},"abstract":[{"lang":"eng","text":"In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core."}]},{"date_updated":"2022-01-06T06:50:50Z","intvolume":"         9","title":"Object-oriented domain specific compilers for programming FPGAs","year":"2001","status":"public","author":[{"last_name":"Mencer","first_name":"Oskar","full_name":"Mencer, Oskar"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"full_name":"Morf, Martin","first_name":"Martin","last_name":"Morf"},{"first_name":"Michael","last_name":"J. Flynn","full_name":"J. Flynn, Michael"}],"doi":"10.1109/92.920835","user_id":"398","volume":9,"page":"205-210","language":[{"iso":"eng"}],"_id":"10713","extern":"1","publication":"{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems","issue":"1","citation":{"short":"O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210.","ama":"Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>. 2001;9(1):205-210. doi:<a href=\"https://doi.org/10.1109/92.920835\">10.1109/92.920835</a>","chicago":"Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. Flynn. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i> 9, no. 1 (2001): 205–10. <a href=\"https://doi.org/10.1109/92.920835\">https://doi.org/10.1109/92.920835</a>.","bibtex":"@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain specific compilers for programming FPGAs}, volume={9}, DOI={<a href=\"https://doi.org/10.1109/92.920835\">10.1109/92.920835</a>}, number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}, year={2001}, pages={205–210} }","apa":"Mencer, O., Platzner, M., Morf, M., &#38; J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>, <i>9</i>(1), 205–210. <a href=\"https://doi.org/10.1109/92.920835\">https://doi.org/10.1109/92.920835</a>","mla":"Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>, vol. 9, no. 1, 2001, pp. 205–10, doi:<a href=\"https://doi.org/10.1109/92.920835\">10.1109/92.920835</a>.","ieee":"O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>, vol. 9, no. 1, pp. 205–210, 2001."},"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T11:47:42Z"},{"department":[{"_id":"78"}],"type":"misc","date_created":"2019-09-30T09:27:00Z","extern":"1","citation":{"ieee":"R. Enzler and M. Platzner, <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","apa":"Enzler, R., &#38; Platzner, M. (2001). <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).","chicago":"Enzler, Rolf, and Marco Platzner. <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","short":"R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","mla":"Enzler, Rolf, and Marco Platzner. <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","bibtex":"@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors}, publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler, Rolf and Platzner, Marco}, year={2001} }","ama":"Enzler R, Platzner M. <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001."},"user_id":"398","_id":"13463","publisher":"TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:36Z","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"status":"public","year":"2001","title":"Dynamically Reconfigurable Processors"},{"citation":{"short":"M. Platzner, Computer 33 (2000) 58–60.","chicago":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” <i>Computer</i> 33, no. 4 (2000): 58–60. <a href=\"https://doi.org/10.1109/2.839322\">https://doi.org/10.1109/2.839322</a>.","apa":"Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. <i>Computer</i>, <i>33</i>(4), 58–60. <a href=\"https://doi.org/10.1109/2.839322\">https://doi.org/10.1109/2.839322</a>","ieee":"M. Platzner, “Reconfigurable accelerators for combinatorial problems,” <i>Computer</i>, vol. 33, no. 4, pp. 58–60, 2000.","ama":"Platzner M. Reconfigurable accelerators for combinatorial problems. <i>Computer</i>. 2000;33(4):58-60. doi:<a href=\"https://doi.org/10.1109/2.839322\">10.1109/2.839322</a>","bibtex":"@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial problems}, volume={33}, DOI={<a href=\"https://doi.org/10.1109/2.839322\">10.1109/2.839322</a>}, number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }","mla":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” <i>Computer</i>, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:<a href=\"https://doi.org/10.1109/2.839322\">10.1109/2.839322</a>."},"volume":33,"user_id":"398","_id":"6507","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","page":"58-60","status":"public","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"type":"journal_article","date_created":"2019-01-08T09:45:03Z","extern":"1","publication":"Computer","issue":"4","doi":"10.1109/2.839322","language":[{"iso":"eng"}],"intvolume":"        33","publication_status":"published","date_updated":"2022-01-06T07:03:08Z","author":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_identifier":{"issn":["0018-9162"]},"title":"Reconfigurable accelerators for combinatorial problems","year":"2000"},{"volume":147,"doi":"10.1049/ip-cdt:20000496","user_id":"398","publisher":"IET","_id":"10606","language":[{"iso":"eng"}],"page":"159-165","intvolume":"       147","date_updated":"2022-01-06T06:50:47Z","author":[{"full_name":"Eisenring, Michael","last_name":"Eisenring","first_name":"Michael"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"year":"2000","status":"public","title":"Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems","department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:22:58Z","extern":"1","citation":{"ama":"Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>. 2000;147:159-165. doi:<a href=\"https://doi.org/10.1049/ip-cdt:20000496\">10.1049/ip-cdt:20000496</a>","bibtex":"@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}, volume={147}, DOI={<a href=\"https://doi.org/10.1049/ip-cdt:20000496\">10.1049/ip-cdt:20000496</a>}, journal={IEE Proceedings -- Computers &#38; Digital Techniques}, publisher={IET}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165} }","mla":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>, vol. 147, IET, 2000, pp. 159–65, doi:<a href=\"https://doi.org/10.1049/ip-cdt:20000496\">10.1049/ip-cdt:20000496</a>.","chicago":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” <i>IEE Proceedings -- Computers &#38; Digital Techniques</i> 147 (2000): 159–65. <a href=\"https://doi.org/10.1049/ip-cdt:20000496\">https://doi.org/10.1049/ip-cdt:20000496</a>.","short":"M. Eisenring, M. Platzner, IEE Proceedings -- Computers &#38; Digital Techniques 147 (2000) 159–165.","apa":"Eisenring, M., &#38; Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>, <i>147</i>, 159–165. <a href=\"https://doi.org/10.1049/ip-cdt:20000496\">https://doi.org/10.1049/ip-cdt:20000496</a>","ieee":"M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>, vol. 147, pp. 159–165, 2000."},"publication":"IEE Proceedings -- Computers & Digital Techniques"},{"_id":"10725","publisher":"Institute of Electrical {\\&} Electronics Engineers ({IEEE})","language":[{"iso":"eng"}],"page":"62-68","volume":15,"doi":"10.1109/5254.850829","user_id":"398","author":[{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Bernhard","last_name":"Rinner","full_name":"Rinner, Bernhard"},{"full_name":"Weiss, Reinhold","first_name":"Reinhold","last_name":"Weiss"}],"title":"Toward embedded qualitative simulation: a specialized computer architecture for QSim","status":"public","year":"2000","intvolume":"        15","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T11:54:17Z","department":[{"_id":"78"}],"type":"journal_article","citation":{"apa":"Platzner, M., Rinner, B., &#38; Weiss, R. (2000). Toward embedded qualitative simulation: a specialized computer architecture for QSim. <i>IEEE Intelligent Systems</i>, <i>15</i>(2), 62–68. <a href=\"https://doi.org/10.1109/5254.850829\">https://doi.org/10.1109/5254.850829</a>","ieee":"M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” <i>IEEE Intelligent Systems</i>, vol. 15, no. 2, pp. 62–68, 2000.","short":"M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems 15 (2000) 62–68.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” <i>IEEE Intelligent Systems</i> 15, no. 2 (2000): 62–68. <a href=\"https://doi.org/10.1109/5254.850829\">https://doi.org/10.1109/5254.850829</a>.","mla":"Platzner, Marco, et al. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” <i>IEEE Intelligent Systems</i>, vol. 15, no. 2, Institute of Electrical {\\&#38;} Electronics Engineers ({IEEE}), 2000, pp. 62–68, doi:<a href=\"https://doi.org/10.1109/5254.850829\">10.1109/5254.850829</a>.","ama":"Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized computer architecture for QSim. <i>IEEE Intelligent Systems</i>. 2000;15(2):62-68. doi:<a href=\"https://doi.org/10.1109/5254.850829\">10.1109/5254.850829</a>","bibtex":"@article{Platzner_Rinner_Weiss_2000, title={Toward embedded qualitative simulation: a specialized computer architecture for QSim}, volume={15}, DOI={<a href=\"https://doi.org/10.1109/5254.850829\">10.1109/5254.850829</a>}, number={2}, journal={IEEE Intelligent Systems}, publisher={Institute of Electrical {\\&#38;} Electronics Engineers ({IEEE})}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={2000}, pages={62–68} }"},"publication":"IEEE Intelligent Systems","issue":"2","extern":"1"},{"publication":"Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)","citation":{"ama":"Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable Systems. In: <i>Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)</i>. 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