[{"abstract":[{"lang":"eng","text":"In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core."}],"citation":{"bibtex":"@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }","ama":"Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>","mla":"Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, vol. 4525, 2001, pp. 135–46, doi:<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>.","short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.","chicago":"Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, 4525:135–46. Proc. SPIE, 2001. <a href=\"https://doi.org/10.1117/12.434376\">https://doi.org/10.1117/12.434376</a>.","ieee":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, 2001, vol. 4525, pp. 135–146.","apa":"Enzler, R., Platzner, M., Plessl, C., Thiele, L., &#38; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i> (Vol. 4525, pp. 135–146). <a href=\"https://doi.org/10.1117/12.434376\">https://doi.org/10.1117/12.434376</a>"},"publication":"Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["benchmark"],"date_created":"2018-04-17T15:51:39Z","intvolume":"      4525","date_updated":"2022-01-06T06:56:17Z","author":[{"full_name":"Enzler, Rolf","last_name":"Enzler","first_name":"Rolf"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Lothar","last_name":"Thiele","full_name":"Thiele, Lothar"},{"first_name":"Gerhard","last_name":"Tröster","full_name":"Tröster, Gerhard"}],"year":"2001","title":"Reconfigurable Processors for Handhelds and Wearables: Application Analysis","status":"public","volume":4525,"user_id":"24135","doi":"10.1117/12.434376","_id":"2432","series_title":"Proc. SPIE","page":"135-146"},{"department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T11:47:42Z","extern":"1","citation":{"bibtex":"@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain specific compilers for programming FPGAs}, volume={9}, DOI={<a href=\"https://doi.org/10.1109/92.920835\">10.1109/92.920835</a>}, number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}, year={2001}, pages={205–210} }","short":"O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210.","ama":"Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>. 2001;9(1):205-210. doi:<a href=\"https://doi.org/10.1109/92.920835\">10.1109/92.920835</a>","chicago":"Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. Flynn. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i> 9, no. 1 (2001): 205–10. <a href=\"https://doi.org/10.1109/92.920835\">https://doi.org/10.1109/92.920835</a>.","ieee":"O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>, vol. 9, no. 1, pp. 205–210, 2001.","mla":"Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>, vol. 9, no. 1, 2001, pp. 205–10, doi:<a href=\"https://doi.org/10.1109/92.920835\">10.1109/92.920835</a>.","apa":"Mencer, O., Platzner, M., Morf, M., &#38; J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. <i>{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems</i>, <i>9</i>(1), 205–210. <a href=\"https://doi.org/10.1109/92.920835\">https://doi.org/10.1109/92.920835</a>"},"publication":"{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems","issue":"1","volume":9,"doi":"10.1109/92.920835","user_id":"398","language":[{"iso":"eng"}],"_id":"10713","page":"205-210","intvolume":"         9","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Mencer","first_name":"Oskar","full_name":"Mencer, Oskar"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"first_name":"Martin","last_name":"Morf","full_name":"Morf, Martin"},{"full_name":"J. Flynn, Michael","first_name":"Michael","last_name":"J. Flynn"}],"title":"Object-oriented domain specific compilers for programming FPGAs","year":"2001","status":"public"},{"_id":"13463","language":[{"iso":"eng"}],"publisher":"TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)","user_id":"398","author":[{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"year":"2001","status":"public","title":"Dynamically Reconfigurable Processors","date_updated":"2022-01-06T06:51:36Z","date_created":"2019-09-30T09:27:00Z","department":[{"_id":"78"}],"type":"misc","citation":{"bibtex":"@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors}, publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler, Rolf and Platzner, Marco}, year={2001} }","ama":"Enzler R, Platzner M. <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.","mla":"Enzler, Rolf, and Marco Platzner. <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","short":"R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","chicago":"Enzler, Rolf, and Marco Platzner. <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","ieee":"R. Enzler and M. Platzner, <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.","apa":"Enzler, R., &#38; Platzner, M. (2001). <i>Dynamically Reconfigurable Processors</i>. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)."},"extern":"1"},{"type":"journal_article","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"date_created":"2019-01-08T09:45:03Z","extern":"1","publication":"Computer","issue":"4","doi":"10.1109/2.839322","language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:03:08Z","publication_status":"published","intvolume":"        33","title":"Reconfigurable accelerators for combinatorial problems","year":"2000","author":[{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"publication_identifier":{"issn":["0018-9162"]},"citation":{"short":"M. Platzner, Computer 33 (2000) 58–60.","chicago":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” <i>Computer</i> 33, no. 4 (2000): 58–60. <a href=\"https://doi.org/10.1109/2.839322\">https://doi.org/10.1109/2.839322</a>.","apa":"Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. <i>Computer</i>, <i>33</i>(4), 58–60. <a href=\"https://doi.org/10.1109/2.839322\">https://doi.org/10.1109/2.839322</a>","ieee":"M. Platzner, “Reconfigurable accelerators for combinatorial problems,” <i>Computer</i>, vol. 33, no. 4, pp. 58–60, 2000.","ama":"Platzner M. Reconfigurable accelerators for combinatorial problems. <i>Computer</i>. 2000;33(4):58-60. doi:<a href=\"https://doi.org/10.1109/2.839322\">10.1109/2.839322</a>","bibtex":"@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial problems}, volume={33}, DOI={<a href=\"https://doi.org/10.1109/2.839322\">10.1109/2.839322</a>}, number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }","mla":"Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” <i>Computer</i>, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:<a href=\"https://doi.org/10.1109/2.839322\">10.1109/2.839322</a>."},"user_id":"398","volume":33,"page":"58-60","_id":"6507","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","status":"public"},{"date_updated":"2022-01-06T06:50:47Z","intvolume":"       147","title":"Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems","status":"public","year":"2000","author":[{"first_name":"Michael","last_name":"Eisenring","full_name":"Eisenring, Michael"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"user_id":"398","doi":"10.1049/ip-cdt:20000496","volume":147,"page":"159-165","publisher":"IET","_id":"10606","language":[{"iso":"eng"}],"extern":"1","publication":"IEE Proceedings -- Computers & Digital Techniques","citation":{"ieee":"M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>, vol. 147, pp. 159–165, 2000.","apa":"Eisenring, M., &#38; Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>, <i>147</i>, 159–165. <a href=\"https://doi.org/10.1049/ip-cdt:20000496\">https://doi.org/10.1049/ip-cdt:20000496</a>","short":"M. Eisenring, M. Platzner, IEE Proceedings -- Computers &#38; Digital Techniques 147 (2000) 159–165.","chicago":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” <i>IEE Proceedings -- Computers &#38; Digital Techniques</i> 147 (2000): 159–65. <a href=\"https://doi.org/10.1049/ip-cdt:20000496\">https://doi.org/10.1049/ip-cdt:20000496</a>.","mla":"Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>, vol. 147, IET, 2000, pp. 159–65, doi:<a href=\"https://doi.org/10.1049/ip-cdt:20000496\">10.1049/ip-cdt:20000496</a>.","bibtex":"@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}, volume={147}, DOI={<a href=\"https://doi.org/10.1049/ip-cdt:20000496\">10.1049/ip-cdt:20000496</a>}, journal={IEE Proceedings -- Computers &#38; Digital Techniques}, publisher={IET}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165} }","ama":"Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. <i>IEE Proceedings -- Computers &#38; Digital Techniques</i>. 2000;147:159-165. doi:<a href=\"https://doi.org/10.1049/ip-cdt:20000496\">10.1049/ip-cdt:20000496</a>"},"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T09:22:58Z"},{"extern":"1","issue":"2","publication":"IEEE Intelligent Systems","citation":{"ama":"Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized computer architecture for QSim. <i>IEEE Intelligent Systems</i>. 2000;15(2):62-68. doi:<a href=\"https://doi.org/10.1109/5254.850829\">10.1109/5254.850829</a>","bibtex":"@article{Platzner_Rinner_Weiss_2000, title={Toward embedded qualitative simulation: a specialized computer architecture for QSim}, volume={15}, DOI={<a href=\"https://doi.org/10.1109/5254.850829\">10.1109/5254.850829</a>}, number={2}, journal={IEEE Intelligent Systems}, publisher={Institute of Electrical {\\&#38;} Electronics Engineers ({IEEE})}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={2000}, pages={62–68} }","mla":"Platzner, Marco, et al. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” <i>IEEE Intelligent Systems</i>, vol. 15, no. 2, Institute of Electrical {\\&#38;} Electronics Engineers ({IEEE}), 2000, pp. 62–68, doi:<a href=\"https://doi.org/10.1109/5254.850829\">10.1109/5254.850829</a>.","short":"M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems 15 (2000) 62–68.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” <i>IEEE Intelligent Systems</i> 15, no. 2 (2000): 62–68. <a href=\"https://doi.org/10.1109/5254.850829\">https://doi.org/10.1109/5254.850829</a>.","apa":"Platzner, M., Rinner, B., &#38; Weiss, R. (2000). Toward embedded qualitative simulation: a specialized computer architecture for QSim. <i>IEEE Intelligent Systems</i>, <i>15</i>(2), 62–68. <a href=\"https://doi.org/10.1109/5254.850829\">https://doi.org/10.1109/5254.850829</a>","ieee":"M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” <i>IEEE Intelligent Systems</i>, vol. 15, no. 2, pp. 62–68, 2000."},"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T11:54:17Z","date_updated":"2022-01-06T06:50:50Z","intvolume":"        15","title":"Toward embedded qualitative simulation: a specialized computer architecture for QSim","year":"2000","status":"public","author":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Bernhard","last_name":"Rinner","full_name":"Rinner, Bernhard"},{"first_name":"Reinhold","last_name":"Weiss","full_name":"Weiss, Reinhold"}],"user_id":"398","doi":"10.1109/5254.850829","volume":15,"page":"62-68","publisher":"Institute of Electrical {\\&} Electronics Engineers ({IEEE})","_id":"10725","language":[{"iso":"eng"}]},{"citation":{"ieee":"M. H. Eisenring and M. Platzner, “An Implementation Framework for Run-time Reconfigurable Systems,” in <i>Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)</i>, 2000, pp. 151–157.","apa":"Eisenring, M. H., &#38; Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In <i>Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)</i> (pp. 151–157). CSREA Press.","chicago":"Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” In <i>Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)</i>, 151–57. CSREA Press, 2000.","short":"M.H. Eisenring, M. Platzner, in: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–157.","mla":"Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” <i>Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)</i>, CSREA Press, 2000, pp. 151–57.","bibtex":"@inproceedings{Eisenring_Platzner_2000, title={An Implementation Framework for Run-time Reconfigurable Systems}, booktitle={Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)}, publisher={CSREA Press}, author={Eisenring, Michael H. and Platzner, Marco}, year={2000}, pages={151–157} }","ama":"Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable Systems. In: <i>Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)</i>. CSREA Press; 2000:151-157."},"publication":"Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)","extern":"1","date_created":"2019-10-04T21:05:39Z","department":[{"_id":"78"}],"type":"conference","author":[{"full_name":"Eisenring, Michael H.","last_name":"Eisenring","first_name":"Michael H."},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"An Implementation Framework for Run-time Reconfigurable Systems","year":"2000","status":"public","date_updated":"2022-01-06T06:51:40Z","_id":"13609","language":[{"iso":"eng"}],"publisher":"CSREA Press","page":"151-157","user_id":"398"},{"language":[{"iso":"eng"}],"_id":"13610","publisher":"Springer","page":"565-574","user_id":"398","author":[{"full_name":"Eisenring, Michael","last_name":"Eisenring","first_name":"Michael"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"status":"public","title":"Optimization of Run-time Reconfigurable Embedded Systems","year":"2000","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T21:09:09Z","department":[{"_id":"78"}],"type":"conference","citation":{"short":"M. Eisenring, M. Platzner, in: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–574.","chicago":"Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” In <i>Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)</i>, 565–74. Springer, 2000.","ieee":"M. Eisenring and M. Platzner, “Optimization of Run-time Reconfigurable Embedded Systems,” in <i>Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)</i>, 2000, pp. 565–574.","apa":"Eisenring, M., &#38; Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In <i>Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)</i> (pp. 565–574). Springer.","bibtex":"@inproceedings{Eisenring_Platzner_2000, title={Optimization of Run-time Reconfigurable Embedded Systems}, booktitle={Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={565–574} }","ama":"Eisenring M, Platzner M. Optimization of Run-time Reconfigurable Embedded Systems. In: <i>Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)</i>. Springer; 2000:565-574.","mla":"Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” <i>Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)</i>, Springer, 2000, pp. 565–74."},"publication":"Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)","extern":"1"},{"extern":"1","publication":"Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)","citation":{"bibtex":"@inproceedings{Mencer_Platzner_1999, title={Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment}, DOI={<a href=\"https://doi.org/10.1109/hicss.1999.772883\">10.1109/hicss.1999.772883</a>}, booktitle={Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)}, publisher={IEEE CS Press}, author={Mencer, Oskar and Platzner, Marco}, year={1999} }","ama":"Mencer O, Platzner M. Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In: <i>Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)</i>. IEEE CS Press; 1999. doi:<a href=\"https://doi.org/10.1109/hicss.1999.772883\">10.1109/hicss.1999.772883</a>","mla":"Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.” <i>Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)</i>, IEEE CS Press, 1999, doi:<a href=\"https://doi.org/10.1109/hicss.1999.772883\">10.1109/hicss.1999.772883</a>.","chicago":"Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.” In <i>Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)</i>. IEEE CS Press, 1999. <a href=\"https://doi.org/10.1109/hicss.1999.772883\">https://doi.org/10.1109/hicss.1999.772883</a>.","short":"O. Mencer, M. Platzner, in: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999.","ieee":"O. Mencer and M. Platzner, “Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment,” in <i>Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)</i>, 1999.","apa":"Mencer, O., &#38; Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In <i>Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)</i>. IEEE CS Press. <a href=\"https://doi.org/10.1109/hicss.1999.772883\">https://doi.org/10.1109/hicss.1999.772883</a>"},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T20:59:20Z","date_updated":"2022-01-06T06:51:40Z","publication_status":"published","status":"public","title":"Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment","year":"1999","author":[{"full_name":"Mencer, Oskar","first_name":"Oskar","last_name":"Mencer"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"publication_identifier":{"isbn":["0769500013"]},"doi":"10.1109/hicss.1999.772883","user_id":"398","_id":"13607","language":[{"iso":"eng"}],"publisher":"IEEE CS Press"},{"date_created":"2019-10-04T21:01:05Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)","extern":"1","series_title":"LCS","language":[{"iso":"eng"}],"doi":"10.1007/978-3-540-48302-1_21","title":"Communication Synthesis for Reconfigurable Embedded Systems","year":"1999","publication_identifier":{"isbn":["9783540664574","9783540483021"],"issn":["0302-9743","1611-3349"]},"author":[{"full_name":"Eisenring, Michael","last_name":"Eisenring","first_name":"Michael"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"date_updated":"2022-01-06T06:51:40Z","publication_status":"published","intvolume":"      1673","citation":{"apa":"Eisenring, M., Platzner, M., &#38; Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In <i>Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)</i> (Vol. 1673, pp. 205–214). Springer. <a href=\"https://doi.org/10.1007/978-3-540-48302-1_21\">https://doi.org/10.1007/978-3-540-48302-1_21</a>","ieee":"M. Eisenring, M. Platzner, and L. Thiele, “Communication Synthesis for Reconfigurable Embedded Systems,” in <i>Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)</i>, 1999, vol. 1673, pp. 205–214.","chicago":"Eisenring, Michael, Marco Platzner, and Lothar Thiele. “Communication Synthesis for Reconfigurable Embedded Systems.” In <i>Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)</i>, 1673:205–14. LCS. Springer, 1999. <a href=\"https://doi.org/10.1007/978-3-540-48302-1_21\">https://doi.org/10.1007/978-3-540-48302-1_21</a>.","short":"M. Eisenring, M. Platzner, L. Thiele, in: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 1999, pp. 205–214.","mla":"Eisenring, Michael, et al. “Communication Synthesis for Reconfigurable Embedded Systems.” <i>Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)</i>, vol. 1673, Springer, 1999, pp. 205–14, doi:<a href=\"https://doi.org/10.1007/978-3-540-48302-1_21\">10.1007/978-3-540-48302-1_21</a>.","ama":"Eisenring M, Platzner M, Thiele L. Communication Synthesis for Reconfigurable Embedded Systems. In: <i>Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)</i>. Vol 1673. LCS. Springer; 1999:205-214. doi:<a href=\"https://doi.org/10.1007/978-3-540-48302-1_21\">10.1007/978-3-540-48302-1_21</a>","bibtex":"@inproceedings{Eisenring_Platzner_Thiele_1999, series={LCS}, title={Communication Synthesis for Reconfigurable Embedded Systems}, volume={1673}, DOI={<a href=\"https://doi.org/10.1007/978-3-540-48302-1_21\">10.1007/978-3-540-48302-1_21</a>}, booktitle={Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Eisenring, Michael and Platzner, Marco and Thiele, Lothar}, year={1999}, pages={205–214}, collection={LCS} }"},"page":"205-214","publisher":"Springer","_id":"13608","user_id":"398","volume":1673,"status":"public"},{"publication":"e&i Elektrotechnik und Informationstechnik","citation":{"ieee":"M. Platzner, “Reconfigurable Computer Architectures,” <i>e&#38;i Elektrotechnik und Informationstechnik</i>, vol. 115, pp. 143–148, 1998.","apa":"Platzner, M. (1998). Reconfigurable Computer Architectures. <i>E&#38;i Elektrotechnik Und Informationstechnik</i>, <i>115</i>, 143–148.","chicago":"Platzner, Marco. “Reconfigurable Computer Architectures.” <i>E&#38;i Elektrotechnik Und Informationstechnik</i> 115 (1998): 143–48.","short":"M. Platzner, E&#38;i Elektrotechnik Und Informationstechnik 115 (1998) 143–148.","mla":"Platzner, Marco. “Reconfigurable Computer Architectures.” <i>E&#38;i Elektrotechnik Und Informationstechnik</i>, vol. 115, Springer, 1998, pp. 143–48.","bibtex":"@article{Platzner_1998, title={Reconfigurable Computer Architectures}, volume={115}, journal={e&#38;i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco}, year={1998}, pages={143–148} }","ama":"Platzner M. Reconfigurable Computer Architectures. <i>e&#38;i Elektrotechnik und Informationstechnik</i>. 1998;115:143-148."},"extern":"1","date_created":"2019-07-10T09:22:59Z","type":"journal_article","department":[{"_id":"78"}],"status":"public","title":"Reconfigurable Computer Architectures","year":"1998","author":[{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:47Z","intvolume":"       115","page":"143-148","language":[{"iso":"eng"}],"_id":"10607","publisher":"Springer","user_id":"398","volume":115},{"department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:23:00Z","extern":"1","citation":{"mla":"Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” <i>International Journal of Computers &#38; Their Applications</i>, vol. 5, ISCA, 1998, pp. 106–16.","bibtex":"@article{Platzner_Rinner_1998, title={Design and Implementation of a Parallel Constraint Satisfaction Algorithm}, volume={5}, journal={International Journal of Computers &#38; Their Applications}, publisher={ISCA}, author={Platzner, Marco and Rinner, Bernhard}, year={1998}, pages={106–116} }","ama":"Platzner M, Rinner B. Design and Implementation of a Parallel Constraint Satisfaction Algorithm. <i>International Journal of Computers &#38; Their Applications</i>. 1998;5:106-116.","ieee":"M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint Satisfaction Algorithm,” <i>International Journal of Computers &#38; Their Applications</i>, vol. 5, pp. 106–116, 1998.","apa":"Platzner, M., &#38; Rinner, B. (1998). Design and Implementation of a Parallel Constraint Satisfaction Algorithm. <i>International Journal of Computers &#38; Their Applications</i>, <i>5</i>, 106–116.","chicago":"Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” <i>International Journal of Computers &#38; Their Applications</i> 5 (1998): 106–16.","short":"M. Platzner, B. Rinner, International Journal of Computers &#38; Their Applications 5 (1998) 106–116."},"publication":"International Journal of Computers & Their Applications","volume":5,"user_id":"398","language":[{"iso":"eng"}],"_id":"10608","publisher":"ISCA","page":"106-116","intvolume":"         5","date_updated":"2022-01-06T06:50:47Z","author":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"last_name":"Rinner","first_name":"Bernhard","full_name":"Rinner, Bernhard"}],"title":"Design and Implementation of a Parallel Constraint Satisfaction Algorithm","status":"public","year":"1998"},{"user_id":"398","publisher":"Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe's leading Universities","_id":"13464","language":[{"iso":"eng"}],"page":"106-107","date_updated":"2022-01-06T06:51:36Z","author":[{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"first_name":"Bernhard","last_name":"Rinner","full_name":"Rinner, Bernhard"},{"full_name":"Weiss, Reinhold","last_name":"Weiss","first_name":"Reinhold"}],"title":"A Distributed Computer Architecture for Fast Qualitative Simulation ","year":"1998","status":"public","department":[{"_id":"78"}],"type":"misc","date_created":"2019-09-30T09:33:27Z","citation":{"short":"M. Platzner, B. Rinner, R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation , Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. <i>A Distributed Computer Architecture for Fast Qualitative Simulation </i>. Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998.","apa":"Platzner, M., Rinner, B., &#38; Weiss, R. (1998). <i>A Distributed Computer Architecture for Fast Qualitative Simulation </i> (pp. 106–107). Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities.","ieee":"M. Platzner, B. Rinner, and R. Weiss, <i>A Distributed Computer Architecture for Fast Qualitative Simulation </i>. Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–107.","ama":"Platzner M, Rinner B, Weiss R. <i>A Distributed Computer Architecture for Fast Qualitative Simulation </i>. Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities; 1998:106-107.","bibtex":"@book{Platzner_Rinner_Weiss_1998, title={A Distributed Computer Architecture for Fast Qualitative Simulation }, publisher={Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1998}, pages={106–107} }","mla":"Platzner, Marco, et al. <i>A Distributed Computer Architecture for Fast Qualitative Simulation </i>. Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–07."}},{"status":"public","user_id":"398","page":"69-78","_id":"13606","publisher":"Springer ","citation":{"apa":"Platzner, M., &#38; De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In <i>Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) </i> (pp. 69–78). Berlin, Heidelberg: Springer . <a href=\"https://doi.org/10.1007/bfb0055234\">https://doi.org/10.1007/bfb0055234</a>","ieee":"M. Platzner and G. De Micheli, “Acceleration of satisfiability algorithms by reconfigurable hardware,” in <i>Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) </i>, 1998, pp. 69–78.","chicago":"Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.” In <i>Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) </i>, 69–78. LNCS. Berlin, Heidelberg: Springer , 1998. <a href=\"https://doi.org/10.1007/bfb0055234\">https://doi.org/10.1007/bfb0055234</a>.","short":"M. Platzner, G. De Micheli, in: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , Berlin, Heidelberg, 1998, pp. 69–78.","mla":"Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.” <i>Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) </i>, Springer , 1998, pp. 69–78, doi:<a href=\"https://doi.org/10.1007/bfb0055234\">10.1007/bfb0055234</a>.","ama":"Platzner M, De Micheli G. Acceleration of satisfiability algorithms by reconfigurable hardware. In: <i>Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) </i>. LNCS. Berlin, Heidelberg: Springer ; 1998:69-78. doi:<a href=\"https://doi.org/10.1007/bfb0055234\">10.1007/bfb0055234</a>","bibtex":"@inproceedings{Platzner_De Micheli_1998, place={Berlin, Heidelberg}, series={LNCS}, title={Acceleration of satisfiability algorithms by reconfigurable hardware}, DOI={<a href=\"https://doi.org/10.1007/bfb0055234\">10.1007/bfb0055234</a>}, booktitle={Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={Springer }, author={Platzner, Marco and De Micheli, Giovanni}, year={1998}, pages={69–78}, collection={LNCS} }"},"place":"Berlin, Heidelberg","date_updated":"2022-01-06T06:51:40Z","publication_status":"published","title":"Acceleration of satisfiability algorithms by reconfigurable hardware","year":"1998","publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783540649489","9783540680666"]},"author":[{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"first_name":"Giovanni","last_name":"De Micheli","full_name":"De Micheli, Giovanni"}],"doi":"10.1007/bfb0055234","language":[{"iso":"eng"}],"series_title":"LNCS","extern":"1","publication":"Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) ","type":"conference","department":[{"_id":"78"}],"date_created":"2019-10-04T20:46:34Z"},{"volume":114,"user_id":"398","_id":"10609","language":[{"iso":"eng"}],"publisher":"Springer","page":"13-18","intvolume":"       114","date_updated":"2022-01-06T06:50:47Z","author":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"first_name":"Bernhard","last_name":"Rinner","full_name":"Rinner, Bernhard"},{"last_name":"Weiss","first_name":"Reinhold","full_name":"Weiss, Reinhold"}],"year":"1997","status":"public","title":"A Computer Architecture to Support Qualitative Simulation in Industrial Applications","department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:23:09Z","extern":"1","citation":{"mla":"Platzner, Marco, et al. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” <i>E &#38; i Elektrotechnik Und Informationstechnik</i>, vol. 114, Springer, 1997, pp. 13–18.","bibtex":"@article{Platzner_Rinner_Weiss_1997, title={A Computer Architecture to Support Qualitative Simulation in Industrial Applications}, volume={114}, journal={e &#38; i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={13–18} }","ama":"Platzner M, Rinner B, Weiss R. A Computer Architecture to Support Qualitative Simulation in Industrial Applications. <i>e &#38; i Elektrotechnik und Informationstechnik</i>. 1997;114:13-18.","ieee":"M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support Qualitative Simulation in Industrial Applications,” <i>e &#38; i Elektrotechnik und Informationstechnik</i>, vol. 114, pp. 13–18, 1997.","apa":"Platzner, M., Rinner, B., &#38; Weiss, R. (1997). A Computer Architecture to Support Qualitative Simulation in Industrial Applications. <i>E &#38; i Elektrotechnik Und Informationstechnik</i>, <i>114</i>, 13–18.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” <i>E &#38; i Elektrotechnik Und Informationstechnik</i> 114 (1997): 13–18.","short":"M. Platzner, B. Rinner, R. Weiss, E &#38; i Elektrotechnik Und Informationstechnik 114 (1997) 13–18."},"publication":"e & i Elektrotechnik und Informationstechnik"},{"citation":{"chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Parallel Qualitative Simulation.” <i>Simulation Practice and Theory</i> 5, no. 7–8 (1997): 623–38. <a href=\"https://doi.org/10.1016/s0928-4869(97)00008-6\">https://doi.org/10.1016/s0928-4869(97)00008-6</a>.","short":"M. Platzner, B. Rinner, R. Weiss, Simulation Practice and Theory 5 (1997) 623–638.","apa":"Platzner, M., Rinner, B., &#38; Weiss, R. (1997). Parallel qualitative simulation. <i>Simulation Practice and Theory</i>, <i>5</i>(7–8), 623–638. <a href=\"https://doi.org/10.1016/s0928-4869(97)00008-6\">https://doi.org/10.1016/s0928-4869(97)00008-6</a>","ieee":"M. Platzner, B. Rinner, and R. Weiss, “Parallel qualitative simulation,” <i>Simulation Practice and Theory</i>, vol. 5, no. 7–8, pp. 623–638, 1997.","ama":"Platzner M, Rinner B, Weiss R. Parallel qualitative simulation. <i>Simulation Practice and Theory</i>. 1997;5(7-8):623-638. doi:<a href=\"https://doi.org/10.1016/s0928-4869(97)00008-6\">10.1016/s0928-4869(97)00008-6</a>","bibtex":"@article{Platzner_Rinner_Weiss_1997, title={Parallel qualitative simulation}, volume={5}, DOI={<a href=\"https://doi.org/10.1016/s0928-4869(97)00008-6\">10.1016/s0928-4869(97)00008-6</a>}, number={7–8}, journal={Simulation Practice and Theory}, publisher={Elsevier}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={623–638} }","mla":"Platzner, Marco, et al. “Parallel Qualitative Simulation.” <i>Simulation Practice and Theory</i>, vol. 5, no. 7–8, Elsevier, 1997, pp. 623–38, doi:<a href=\"https://doi.org/10.1016/s0928-4869(97)00008-6\">10.1016/s0928-4869(97)00008-6</a>."},"issue":"7-8","publication":"Simulation Practice and Theory","extern":"1","date_created":"2019-07-10T11:54:16Z","department":[{"_id":"78"}],"type":"journal_article","author":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Bernhard","last_name":"Rinner","full_name":"Rinner, Bernhard"},{"last_name":"Weiss","first_name":"Reinhold","full_name":"Weiss, Reinhold"}],"title":"Parallel qualitative simulation","year":"1997","status":"public","intvolume":"         5","date_updated":"2022-01-06T06:50:50Z","_id":"10724","publisher":"Elsevier","language":[{"iso":"eng"}],"page":"623-638","volume":5,"doi":"10.1016/s0928-4869(97)00008-6","user_id":"398"},{"volume":3166,"user_id":"398","language":[{"iso":"eng"}],"_id":"13603","intvolume":"      3166","date_updated":"2022-01-06T06:51:40Z","author":[{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"first_name":"Liliane","last_name":"Peters","full_name":"Peters, Liliane"}],"year":"1997","title":"Fast Signature Segmentation on a Multi-DSP Architecture","status":"public","department":[{"_id":"78"}],"type":"conference","date_created":"2019-10-04T20:40:55Z","extern":"1","citation":{"mla":"Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” <i>Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing</i>, vol. 3166, 1997.","ama":"Platzner M, Peters L. Fast Signature Segmentation on a Multi-DSP Architecture. In: <i>Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing</i>. Vol 3166. ; 1997.","bibtex":"@inproceedings{Platzner_Peters_1997, title={Fast Signature Segmentation on a Multi-DSP Architecture}, volume={3166}, booktitle={Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing}, author={Platzner, Marco and Peters, Liliane}, year={1997} }","apa":"Platzner, M., &#38; Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In <i>Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing</i> (Vol. 3166).","ieee":"M. Platzner and L. Peters, “Fast Signature Segmentation on a Multi-DSP Architecture,” in <i>Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing</i>, 1997, vol. 3166.","chicago":"Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” In <i>Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing</i>, Vol. 3166, 1997.","short":"M. Platzner, L. Peters, in: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997."},"publication":"Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing"},{"citation":{"bibtex":"@inproceedings{Röwekamp_Platzner_Peters_1997, title={Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP}, booktitle={Proceedings of the 8th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)}, author={Röwekamp, Thomas and Platzner, Marco and Peters, Liliane }, year={1997}, pages={829–833} }","ama":"Röwekamp T, Platzner M, Peters L. Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In: <i>Proceedings of the 8th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>. ; 1997:829-833.","mla":"Röwekamp, Thomas, et al. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” <i>Proceedings of the 8th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>, 1997, pp. 829–33.","short":"T. Röwekamp, M. Platzner, L. Peters, in: Proceedings of the 8th International Conference on Signal Processing Applications &#38; Technology (ICSPAT), 1997, pp. 829–833.","chicago":"Röwekamp, Thomas, Marco Platzner, and Liliane  Peters. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” In <i>Proceedings of the 8th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>, 829–33, 1997.","ieee":"T. Röwekamp, M. Platzner, and L. Peters, “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP,” in <i>Proceedings of the 8th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>, 1997, pp. 829–833.","apa":"Röwekamp, T., Platzner, M., &#38; Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In <i>Proceedings of the 8th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i> (pp. 829–833)."},"publication":"Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT)","extern":"1","date_created":"2019-10-04T20:43:29Z","department":[{"_id":"78"}],"type":"conference","author":[{"full_name":"Röwekamp, Thomas","first_name":"Thomas","last_name":"Röwekamp"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"full_name":"Peters, Liliane ","last_name":"Peters","first_name":"Liliane "}],"year":"1997","title":"Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP","status":"public","date_updated":"2022-01-06T06:51:40Z","_id":"13604","language":[{"iso":"eng"}],"page":"829-833","user_id":"398"},{"date_created":"2019-10-04T20:37:59Z","type":"conference","department":[{"_id":"78"}],"publication":"Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT)","citation":{"short":"E. Lind, M. Platzner, B. Rinner, in: Proceedings of the 7th International Conference on Signal Processing Applications &#38; Technology (ICSPAT), 1996.","chicago":"Lind, Erich, Marco Platzner, and Bernhard  Rinner. “A Multi-DSP System with Dynamically Reconfigurable Processors.” In <i>Proceedings of the 7th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>, 1996.","ieee":"E. Lind, M. Platzner, and B. Rinner, “A Multi-DSP System with Dynamically Reconfigurable Processors,” in <i>Proceedings of the 7th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>, 1996.","apa":"Lind, E., Platzner, M., &#38; Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In <i>Proceedings of the 7th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>.","bibtex":"@inproceedings{Lind_Platzner_Rinner_1996, title={A Multi-DSP System with Dynamically Reconfigurable Processors}, booktitle={Proceedings of the 7th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)}, author={Lind, Erich and Platzner, Marco and Rinner, Bernhard }, year={1996} }","ama":"Lind E, Platzner M, Rinner B. A Multi-DSP System with Dynamically Reconfigurable Processors. In: <i>Proceedings of the 7th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>. ; 1996.","mla":"Lind, Erich, et al. “A Multi-DSP System with Dynamically Reconfigurable Processors.” <i>Proceedings of the 7th International Conference on Signal Processing Applications &#38; Technology (ICSPAT)</i>, 1996."},"extern":"1","_id":"13602","language":[{"iso":"eng"}],"user_id":"398","year":"1996","title":"A Multi-DSP System with Dynamically Reconfigurable Processors","status":"public","author":[{"first_name":"Erich","last_name":"Lind","full_name":"Lind, Erich"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"first_name":"Bernhard ","last_name":"Rinner","full_name":"Rinner, Bernhard "}],"date_updated":"2022-01-06T06:51:40Z"},{"extern":"1","publication":"J.UCS Journal of Universal Computer Science","citation":{"mla":"Platzner, Marco, et al. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” <i>J.UCS Journal of Universal Computer Science</i>, vol. 12, Springer, 1995, pp. 811–20.","ama":"Platzner M, Rinner B, Weiss R. Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. <i>JUCS Journal of Universal Computer Science</i>. 1995;12:811-820.","bibtex":"@article{Platzner_Rinner_Weiss_1995, title={Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation}, volume={12}, journal={J.UCS Journal of Universal Computer Science}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1995}, pages={811–820} }","apa":"Platzner, M., Rinner, B., &#38; Weiss, R. (1995). Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. <i>J.UCS Journal of Universal Computer Science</i>, <i>12</i>, 811–820.","ieee":"M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation,” <i>J.UCS Journal of Universal Computer Science</i>, vol. 12, pp. 811–820, 1995.","short":"M. Platzner, B. Rinner, R. Weiss, J.UCS Journal of Universal Computer Science 12 (1995) 811–820.","chicago":"Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” <i>J.UCS Journal of Universal Computer Science</i> 12 (1995): 811–20."},"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T09:23:10Z","date_updated":"2022-01-06T06:50:47Z","intvolume":"        12","title":"Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation","status":"public","year":"1995","author":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Bernhard","last_name":"Rinner","full_name":"Rinner, Bernhard"},{"last_name":"Weiss","first_name":"Reinhold","full_name":"Weiss, Reinhold"}],"user_id":"398","volume":12,"page":"811-820","_id":"10610","language":[{"iso":"eng"}],"publisher":"Springer"}]