[{"supervisor":[{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"citation":{"mla":"Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany, 2022, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>.","bibtex":"@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>}, publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab}, year={2022} }","ama":"Ahmed QA. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany; 2022. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>","ieee":"Q. A. Ahmed, <i>Hardware Trojans in Reconfigurable Computing</i>. Paderborn:  Paderborn University, Paderborn, Germany, 2022.","apa":"Ahmed, Q. A. (2022). <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany. <a href=\"https://doi.org/10.17619/UNIPB/1-1271\">https://doi.org/10.17619/UNIPB/1-1271</a>","short":"Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing,  Paderborn University, Paderborn, Germany, Paderborn, 2022.","chicago":"Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>. Paderborn:  Paderborn University, Paderborn, Germany, 2022. <a href=\"https://doi.org/10.17619/UNIPB/1-1271\">https://doi.org/10.17619/UNIPB/1-1271</a>."},"project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"place":"Paderborn","oa":"1","status":"public","has_accepted_license":"1","_id":"29769","publisher":" Paderborn University, Paderborn, Germany","ddc":["004"],"user_id":"477","abstract":[{"text":"Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.","lang":"eng"},{"lang":"eng","text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable systems, the defenders perspective which corresponds to the bitstream-level Trojan detection technique, and the attackers perspective which corresponds to a novel FPGA Trojan attack. From the defender's perspective, we introduce a first-ever successful pre-configuration countermeasure against the ``Malicious LUT''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers perspective, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by bitstream-level verification techniques."}],"date_created":"2022-02-07T14:02:36Z","keyword":["FPGA Security","Hardware Trojans","Bitstream-level Trojans","Bitstream Verification"],"type":"dissertation","department":[{"_id":"78"}],"title":"Hardware Trojans in Reconfigurable Computing","year":"2022","author":[{"id":"72764","full_name":"Ahmed, Qazi Arbab","orcid":"0000-0002-1837-2254","last_name":"Ahmed","first_name":"Qazi Arbab"}],"date_updated":"2022-11-30T13:39:01Z","publication_status":"published","main_file_link":[{"open_access":"1","url":"\turn:nbn:de:hbz:466:2-40303"}],"language":[{"iso":"eng"}],"doi":"10.17619/UNIPB/1-1271"},{"citation":{"ieee":"C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.” 2022.","apa":"Lienen, C., &#38; Platzner, M. (2022). <i>ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications</i>.","short":"C. Lienen, M. Platzner, (2022).","chicago":"Lienen, Christian, and Marco Platzner. “ReconROS Executor: Event-Driven Programming of FPGA-Accelerated ROS 2 Applications,” 2022.","mla":"Lienen, Christian, and Marco Platzner. <i>ReconROS Executor: Event-Driven Programming of FPGA-Accelerated ROS 2 Applications</i>. 2022.","bibtex":"@article{Lienen_Platzner_2022, title={ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications}, author={Lienen, Christian and Platzner, Marco}, year={2022} }","ama":"Lienen C, Platzner M. ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications. Published online 2022."},"date_created":"2022-01-26T08:52:20Z","type":"preprint","department":[{"_id":"78"}],"status":"public","year":"2022","title":"ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications","author":[{"id":"60323","full_name":"Lienen, Christian","last_name":"Lienen","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2022-01-28T08:30:16Z","main_file_link":[{"url":"https://arxiv.org/abs/2201.07454"}],"language":[{"iso":"eng"}],"_id":"29541","user_id":"60323"},{"author":[{"id":"60323","first_name":"Christian","last_name":"Lienen","full_name":"Lienen, Christian"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"conference":{"name":"2022 Sixth IEEE International Conference on Robotic Computing (IRC) ","location":"Neaples, Italy"},"title":"Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS","status":"public","year":"2022","publication_status":"accepted","date_updated":"2022-11-04T09:26:47Z","language":[{"iso":"eng"}],"_id":"34007","user_id":"60323","citation":{"chicago":"Lienen, Christian, and Marco Platzner. “Task Mapping for Hardware-Accelerated Robotics Applications Using ReconROS,” n.d.","short":"C. Lienen, M. Platzner, in: n.d.","ieee":"C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.","apa":"Lienen, C., &#38; Platzner, M. (n.d.). <i>Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS</i>. 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.","bibtex":"@inproceedings{Lienen_Platzner, title={Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS}, author={Lienen, Christian and Platzner, Marco} }","ama":"Lienen C, Platzner M. Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS.","mla":"Lienen, Christian, and Marco Platzner. <i>Task Mapping for Hardware-Accelerated Robotics Applications Using ReconROS</i>."},"date_created":"2022-11-04T09:26:42Z","department":[{"_id":"78"}],"type":"conference"},{"publication":"2022 25th Euromicro Conference on Digital System Design (DSD)","citation":{"ieee":"C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,” presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi: <a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>.","apa":"Lienen, C., &#38; Platzner, M. (n.d.). Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>. 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain. <a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">https://doi.org/10.1109/DSD57027.2022.00088</a>","chicago":"Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated ROS 2 Robotics Applications.” In <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>, n.d. <a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">https://doi.org/10.1109/DSD57027.2022.00088</a>.","short":"C. Lienen, M. Platzner, in: 2022 25th Euromicro Conference on Digital System Design (DSD), n.d.","mla":"Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated ROS 2 Robotics Applications.” <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>, doi:<a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>.","bibtex":"@inproceedings{Lienen_Platzner, title={Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications}, DOI={<a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>}, booktitle={2022 25th Euromicro Conference on Digital System Design (DSD)}, author={Lienen, Christian and Platzner, Marco} }","ama":"Lienen C, Platzner M. Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. In: <i>2022 25th Euromicro Conference on Digital System Design (DSD)</i>. doi:<a href=\"https://doi.org/10.1109/DSD57027.2022.00088\">10.1109/DSD57027.2022.00088</a>"},"date_created":"2022-11-04T09:24:47Z","type":"conference","department":[{"_id":"78"}],"title":"Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications","year":"2022","status":"public","conference":{"name":"25th Euromicro Conference on Digital System Design (DSD)","location":"Maspalomas, Gran Canaria, Spain"},"author":[{"first_name":"Christian","last_name":"Lienen","full_name":"Lienen, Christian","id":"60323"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2023-01-06T06:38:27Z","publication_status":"accepted","language":[{"iso":"eng"}],"_id":"34005","doi":"10.1109/DSD57027.2022.00088","user_id":"60323"},{"user_id":"15504","doi":"10.17619/UNIPB/1-1649","_id":"34041","language":[{"iso":"eng"}],"date_updated":"2023-01-19T06:41:22Z","title":"Frameworks and Methodologies for Search-based Approximate Logic Synthesis","status":"public","year":"2022","author":[{"full_name":"Witschen, Linus Matthias","last_name":"Witschen","first_name":"Linus Matthias","id":"49051"}],"type":"dissertation","department":[{"_id":"78"}],"date_created":"2022-11-09T06:26:22Z","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"name":"SFB 901 - B: SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901 - B4: SFB 901 - Subproject B4","_id":"12"}],"citation":{"mla":"Witschen, Linus Matthias. <i>Frameworks and Methodologies for Search-Based Approximate Logic Synthesis</i>. 2022, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1649\">10.17619/UNIPB/1-1649</a>.","bibtex":"@book{Witschen_2022, title={Frameworks and Methodologies for Search-based Approximate Logic Synthesis}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1649\">10.17619/UNIPB/1-1649</a>}, author={Witschen, Linus Matthias}, year={2022} }","ama":"Witschen LM. <i>Frameworks and Methodologies for Search-Based Approximate Logic Synthesis</i>.; 2022. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1649\">10.17619/UNIPB/1-1649</a>","ieee":"L. M. Witschen, <i>Frameworks and Methodologies for Search-based Approximate Logic Synthesis</i>. 2022.","apa":"Witschen, L. M. (2022). <i>Frameworks and Methodologies for Search-based Approximate Logic Synthesis</i>. <a href=\"https://doi.org/10.17619/UNIPB/1-1649\">https://doi.org/10.17619/UNIPB/1-1649</a>","chicago":"Witschen, Linus Matthias. <i>Frameworks and Methodologies for Search-Based Approximate Logic Synthesis</i>, 2022. <a href=\"https://doi.org/10.17619/UNIPB/1-1649\">https://doi.org/10.17619/UNIPB/1-1649</a>.","short":"L.M. Witschen, Frameworks and Methodologies for Search-Based Approximate Logic Synthesis, 2022."},"supervisor":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}]},{"date_updated":"2023-04-19T15:04:30Z","author":[{"full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed","orcid":"0000-0002-1837-2254","first_name":"Qazi Arbab","id":"72764"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"conference":{"end_date":"July 6, 2022","name":"IEEE Computer Society Annual Symposium on VLSI Aliathon Resort,","start_date":" July 4, 2022","location":"Pafos, Cyprus"},"title":"On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs","status":"public","year":"2022","user_id":"72764","language":[{"iso":"eng"}],"_id":"32342","publisher":"IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"name":"SFB 901 - B4: SFB 901 - Subproject B4","_id":"12"}],"citation":{"mla":"Ahmed, Qazi Arbab, and Marco Platzner. <i>On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs</i>. IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), 2022.","ama":"Ahmed QA, Platzner M. On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022); 2022.","bibtex":"@inproceedings{Ahmed_Platzner_2022, place={Pafos, Cyprus}, title={On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs}, publisher={IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)}, author={Ahmed, Qazi Arbab and Platzner, Marco}, year={2022} }","apa":"Ahmed, Q. A., &#38; Platzner, M. (2022). <i>On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs</i>. IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus.","ieee":"Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus, 2022.","chicago":"Ahmed, Qazi Arbab, and Marco Platzner. “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs.” Pafos, Cyprus: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), 2022.","short":"Q.A. Ahmed, M. Platzner, in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), Pafos, Cyprus, 2022."},"department":[{"_id":"78"}],"type":"conference","date_created":"2022-07-12T19:56:48Z","place":"Pafos, Cyprus"},{"citation":{"ama":"Jentzsch F, Umuroglu Y, Pappalardo A, Blott M, Platzner M. RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. <i>IEEE Micro</i>. 2022;42(6):125-133. doi:<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>","bibtex":"@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}, volume={42}, DOI={<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>}, number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}, year={2022}, pages={125–133} }","mla":"Jentzsch, Felix, et al. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” <i>IEEE Micro</i>, vol. 42, no. 6, IEEE, 2022, pp. 125–33, doi:<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>.","chicago":"Jentzsch, Felix, Yaman Umuroglu, Alessandro Pappalardo, Michaela Blott, and Marco Platzner. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” <i>IEEE Micro</i> 42, no. 6 (2022): 125–33. <a href=\"https://doi.org/10.1109/MM.2022.3202091\">https://doi.org/10.1109/MM.2022.3202091</a>.","short":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro 42 (2022) 125–133.","apa":"Jentzsch, F., Umuroglu, Y., Pappalardo, A., Blott, M., &#38; Platzner, M. (2022). RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. <i>IEEE Micro</i>, <i>42</i>(6), 125–133. <a href=\"https://doi.org/10.1109/MM.2022.3202091\">https://doi.org/10.1109/MM.2022.3202091</a>","ieee":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,” <i>IEEE Micro</i>, vol. 42, no. 6, pp. 125–133, 2022, doi: <a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>."},"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"33990","publisher":"IEEE","page":"125-133","volume":42,"user_id":"55631","status":"public","date_created":"2022-11-03T14:42:16Z","department":[{"_id":"78"}],"type":"journal_article","publication":"IEEE Micro","issue":"6","abstract":[{"lang":"eng","text":"Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes."}],"language":[{"iso":"eng"}],"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9933377"}],"doi":"10.1109/MM.2022.3202091","author":[{"id":"55631","full_name":"Jentzsch, Felix","first_name":"Felix","orcid":"0000-0003-4987-5708","last_name":"Jentzsch"},{"last_name":"Umuroglu","first_name":"Yaman","full_name":"Umuroglu, Yaman"},{"first_name":"Alessandro","last_name":"Pappalardo","full_name":"Pappalardo, Alessandro"},{"full_name":"Blott, Michaela","last_name":"Blott","first_name":"Michaela"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"year":"2022","title":"RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures","intvolume":"        42","date_updated":"2023-04-04T15:09:17Z","publication_status":"published"},{"project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"grant_number":"160364472","_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "}],"supervisor":[{"id":"74287","full_name":"Clausing, Lennart","last_name":"Clausing","first_name":"Lennart","orcid":"0000-0003-3789-6034"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"id":"209","orcid":"0000-0002-3717-3939","first_name":"Sybille","last_name":"Hellebrand","full_name":"Hellebrand, Sybille"}],"citation":{"chicago":"Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>, 2022.","short":"V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators, 2022.","ieee":"V. I. Tcheussi Ngayap, <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>. 2022.","apa":"Tcheussi Ngayap, V. I. (2022). <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>.","bibtex":"@book{Tcheussi Ngayap_2022, title={FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators}, author={Tcheussi Ngayap, Vanessa Ingrid}, year={2022} }","ama":"Tcheussi Ngayap VI. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>.; 2022.","mla":"Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>. 2022."},"department":[{"_id":"78"}],"type":"mastersthesis","date_created":"2023-06-22T12:04:57Z","date_updated":"2023-06-22T12:07:53Z","author":[{"full_name":"Tcheussi Ngayap, Vanessa Ingrid","first_name":"Vanessa Ingrid","last_name":"Tcheussi Ngayap"}],"year":"2022","status":"public","title":"FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators","user_id":"74287","_id":"45715","language":[{"iso":"eng"}]},{"date_updated":"2023-07-09T13:05:11Z","year":"2022","status":"public","title":"Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance","author":[{"full_name":"Manjunatha, Suraj","first_name":"Suraj","last_name":"Manjunatha"}],"user_id":"398","language":[{"iso":"eng"}],"_id":"45914","publisher":"Paderborn University ","project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"_id":"82","name":"SFB 901 - T: SFB 901 - Project Area T"},{"_id":"1","grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "}],"citation":{"mla":"Manjunatha, Suraj. <i>Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance</i>. Paderborn University , 2022.","ama":"Manjunatha S. <i>Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance</i>. Paderborn University ; 2022.","bibtex":"@book{Manjunatha_2022, title={Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance}, publisher={Paderborn University }, author={Manjunatha, Suraj}, year={2022} }","apa":"Manjunatha, S. (2022). <i>Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance</i>. Paderborn University .","ieee":"S. Manjunatha, <i>Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance</i>. Paderborn University , 2022.","chicago":"Manjunatha, Suraj. <i>Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance</i>. Paderborn University , 2022.","short":"S. Manjunatha, Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In  Predictive Maintenance, Paderborn University , 2022."},"supervisor":[{"last_name":"Platzner","first_name":"Marco ","full_name":"Platzner, Marco "}],"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2023-07-09T12:54:08Z"},{"user_id":"398","language":[{"iso":"eng"}],"_id":"45915","date_updated":"2023-07-09T13:05:55Z","title":"Analysis of Time-Series Classification in Conditional Monitoring Systems","year":"2022","status":"public","author":[{"full_name":"Kaur , Parvinder","last_name":"Kaur ","first_name":"Parvinder"}],"type":"mastersthesis","department":[{"_id":"78"}],"place":"Paderborn University ","date_created":"2023-07-09T12:58:06Z","project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"grant_number":"160364472","_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "}],"supervisor":[{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"citation":{"mla":"Kaur , Parvinder. <i>Analysis of Time-Series Classification in Conditional Monitoring Systems</i>. 2022.","bibtex":"@book{Kaur _2022, place={Paderborn University }, title={Analysis of Time-Series Classification in Conditional Monitoring Systems}, author={Kaur , Parvinder}, year={2022} }","ama":"Kaur  P. <i>Analysis of Time-Series Classification in Conditional Monitoring Systems</i>.; 2022.","ieee":"P. Kaur , <i>Analysis of Time-Series Classification in Conditional Monitoring Systems</i>. Paderborn University , 2022.","apa":"Kaur , P. (2022). <i>Analysis of Time-Series Classification in Conditional Monitoring Systems</i>.","chicago":"Kaur , Parvinder. <i>Analysis of Time-Series Classification in Conditional Monitoring Systems</i>. Paderborn University , 2022.","short":"P. Kaur , Analysis of Time-Series Classification in Conditional Monitoring Systems, Paderborn University , 2022."}},{"doi":"10.1109/vlsi-soc54400.2022.9939606","user_id":"64665","_id":"64115","publisher":"IEEE","date_updated":"2026-02-11T10:20:33Z","publication_status":"published","author":[{"first_name":"Muhammad","last_name":"Awais","full_name":"Awais, Muhammad"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"title":"Automated Framework for Fast Synthesis of Approximate Hardware Accelerators","status":"public","year":"2022","department":[{"_id":"78"}],"type":"conference","date_created":"2026-02-11T10:20:04Z","citation":{"mla":"Awais, Muhammad, and Marco Platzner. “Automated Framework for Fast Synthesis of Approximate Hardware Accelerators.” <i>2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)</i>, IEEE, 2022, doi:<a href=\"https://doi.org/10.1109/vlsi-soc54400.2022.9939606\">10.1109/vlsi-soc54400.2022.9939606</a>.","bibtex":"@inproceedings{Awais_Platzner_2022, title={Automated Framework for Fast Synthesis of Approximate Hardware Accelerators}, DOI={<a href=\"https://doi.org/10.1109/vlsi-soc54400.2022.9939606\">10.1109/vlsi-soc54400.2022.9939606</a>}, booktitle={2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)}, publisher={IEEE}, author={Awais, Muhammad and Platzner, Marco}, year={2022} }","ama":"Awais M, Platzner M. Automated Framework for Fast Synthesis of Approximate Hardware Accelerators. In: <i>2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)</i>. IEEE; 2022. doi:<a href=\"https://doi.org/10.1109/vlsi-soc54400.2022.9939606\">10.1109/vlsi-soc54400.2022.9939606</a>","ieee":"M. Awais and M. Platzner, “Automated Framework for Fast Synthesis of Approximate Hardware Accelerators,” 2022, doi: <a href=\"https://doi.org/10.1109/vlsi-soc54400.2022.9939606\">10.1109/vlsi-soc54400.2022.9939606</a>.","apa":"Awais, M., &#38; Platzner, M. (2022). Automated Framework for Fast Synthesis of Approximate Hardware Accelerators. <i>2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)</i>. <a href=\"https://doi.org/10.1109/vlsi-soc54400.2022.9939606\">https://doi.org/10.1109/vlsi-soc54400.2022.9939606</a>","chicago":"Awais, Muhammad, and Marco Platzner. “Automated Framework for Fast Synthesis of Approximate Hardware Accelerators.” In <i>2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)</i>. IEEE, 2022. <a href=\"https://doi.org/10.1109/vlsi-soc54400.2022.9939606\">https://doi.org/10.1109/vlsi-soc54400.2022.9939606</a>.","short":"M. Awais, M. Platzner, in: 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, 2022."},"publication":"2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"},{"abstract":[{"lang":"eng","text":"Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques."},{"text":"Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen, Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale. Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt werden können.","lang":"ger"}],"keyword":["Proof-Carrying Hardware","Formal Verification","Sequential Circuits","Non-Functional Properties","Functional Properties"],"type":"dissertation","department":[{"_id":"78"}],"date_created":"2021-10-25T06:35:41Z","date_updated":"2022-01-06T06:57:26Z","publication_status":"published","title":"Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware","year":"2021","author":[{"id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias"}],"main_file_link":[{"open_access":"1","url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800"}],"language":[{"iso":"eng"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - Subproject B4"}],"supervisor":[{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"citation":{"short":"T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.","chicago":"Wiersema, Tobias. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn: Paderborn University, 2021.","apa":"Wiersema, T. (2021). <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn University.","ieee":"T. Wiersema, <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn: Paderborn University, 2021.","ama":"Wiersema T. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn University; 2021.","bibtex":"@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2021} }","mla":"Wiersema, Tobias. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn University, 2021."},"oa":"1","place":"Paderborn","status":"public","ddc":["006"],"user_id":"3118","page":"293","_id":"26746","publisher":"Paderborn University"},{"date_updated":"2022-01-06T06:58:46Z","publication_status":"published","author":[{"full_name":"Lienen, Christian","first_name":"Christian","last_name":"Lienen","id":"60323"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"publication_identifier":{"issn":["1936-7406","1936-7414"]},"year":"2021","status":"public","title":"Design of Distributed Reconfigurable Robotics Systems with ReconROS","doi":"10.1145/3494571","user_id":"60323","_id":"29150","language":[{"iso":"eng"}],"page":"1-20","abstract":[{"text":"Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.","lang":"eng"}],"citation":{"mla":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2021, pp. 1–20, doi:<a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>.","ama":"Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. Published online 2021:1-20. doi:<a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>","bibtex":"@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable Robotics Systems with ReconROS}, DOI={<a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Lienen, Christian and Platzner, Marco}, year={2021}, pages={1–20} }","apa":"Lienen, C., &#38; Platzner, M. (2021). Design of Distributed Reconfigurable Robotics Systems with ReconROS. <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 1–20. <a href=\"https://doi.org/10.1145/3494571\">https://doi.org/10.1145/3494571</a>","ieee":"C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, pp. 1–20, 2021, doi: <a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>.","chicago":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2021, 1–20. <a href=\"https://doi.org/10.1145/3494571\">https://doi.org/10.1145/3494571</a>.","short":"C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (2021) 1–20."},"publication":"ACM Transactions on Reconfigurable Technology and Systems","department":[{"_id":"78"}],"type":"journal_article","date_created":"2022-01-04T08:30:10Z"},{"language":[{"iso":"eng"}],"_id":"29151","publisher":"Paderborn University","user_id":"49992","year":"2021","status":"public","title":"A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes","author":[{"full_name":"Kashikar, Chinmay","first_name":"Chinmay","last_name":"Kashikar"}],"date_updated":"2022-01-06T06:58:46Z","place":"Paderborn","date_created":"2022-01-04T09:24:52Z","type":"mastersthesis","department":[{"_id":"78"}],"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"id":"49992","first_name":"Tim","last_name":"Hansmeier","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim"}],"citation":{"bibtex":"@book{Kashikar_2021, place={Paderborn}, title={A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes}, publisher={Paderborn University}, author={Kashikar, Chinmay}, year={2021} }","ama":"Kashikar C. <i>A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn University; 2021.","mla":"Kashikar, Chinmay. <i>A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn University, 2021.","chicago":"Kashikar, Chinmay. <i>A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn: Paderborn University, 2021.","short":"C. Kashikar, A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes, Paderborn University, Paderborn, 2021.","ieee":"C. Kashikar, <i>A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn: Paderborn University, 2021.","apa":"Kashikar, C. (2021). <i>A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn University."},"abstract":[{"lang":"eng","text":"Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique."}],"project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"}]},{"conference":{"location":"Virtual","start_date":"2021-06-22","name":"31st ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021","end_date":"2021-06-25"},"author":[{"orcid":"https://orcid.org/0000-0003-4148-2969","first_name":"Muhammad","last_name":"Awais","full_name":"Awais, Muhammad","id":"64665"},{"id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis","status":"public","year":"2021","date_updated":"2022-01-06T06:55:07Z","publication_status":"published","_id":"21610","publisher":"ACM","language":[{"iso":"eng"}],"page":"27-32","doi":"https://doi.org/10.1145/3453688.3461506","user_id":"64665","citation":{"apa":"Awais, M., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2021). LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i> (pp. 27–32). Virtual: ACM. <a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>, Virtual, 2021, pp. 27–32.","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “LDAX: A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.” In <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>, 27–32. ACM, 2021. <a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32.","mla":"Awais, Muhammad, et al. “LDAX: A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.” <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>, ACM, 2021, pp. 27–32, doi:<a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>.","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In: <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>. ACM; 2021:27-32. doi:<a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2021, title={LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis}, DOI={<a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>}, booktitle={Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2021}, pages={27–32} }"},"publication":"Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021","date_created":"2021-04-13T10:17:47Z","department":[{"_id":"78"}],"type":"conference"},{"title":"Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib","year":"2021","status":"public","author":[{"last_name":"Rehnen","first_name":"Jakob Werner","full_name":"Rehnen, Jakob Werner"}],"date_updated":"2022-01-06T06:55:29Z","language":[{"iso":"eng"}],"_id":"22216","user_id":"49051","supervisor":[{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"id":"49051","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias","last_name":"Witschen"}],"citation":{"bibtex":"@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner}, year={2021} }","ama":"Rehnen JW. <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>.; 2021.","mla":"Rehnen, Jakob Werner. <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>. 2021.","chicago":"Rehnen, Jakob Werner. <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>, 2021.","short":"J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib, 2021.","ieee":"J. W. Rehnen, <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>. 2021.","apa":"Rehnen, J. W. (2021). <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>."},"date_created":"2021-05-19T16:56:11Z","type":"bachelorsthesis","department":[{"_id":"78"},{"_id":"7"}]},{"date_updated":"2022-01-06T06:55:31Z","author":[{"id":"64665","orcid":"https://orcid.org/0000-0003-4148-2969","last_name":"Awais","first_name":"Muhammad","full_name":"Awais, Muhammad"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"conference":{"start_date":"2021-07-07","name":"IEEE Computer Society Annual Symposium on VLSI","location":"Tampa, Florida USA (Virtual)","end_date":"2021-07-09"},"title":"MCTS-Based Synthesis Towards Efficient Approximate Accelerators","year":"2021","status":"public","user_id":"64665","language":[{"iso":"eng"}],"_id":"22309","publisher":"IEEE","page":"384-389","abstract":[{"text":"Approximate computing (AC) has acquired significant maturity in recent years as a promising approach to obtain energy and area-efficient hardware. Automated approximate accelerator synthesis involves a great deal of complexity on the size of design space which exponentially grows with the number of possible approximations. Design space exploration of approximate accelerator synthesis is usually targeted via heuristic-based search methods. The majority of existing frameworks prune a large part of the design space using a greedy-based approach to keep the problem tractable. Therefore, they result in inferior solutions since many potential solutions are neglected in the pruning process without the possibility of backtracking of removed approximate instances. In this paper, we address the aforementioned issue by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based search algorithm, in the context of automated synthesis of approximate accelerators. This enables the synthesis frameworks to deeply subsamples the design space of approximate accelerator synthesis toward most promising approximate instances based on the required performance goals, i.e., power consumption, area, or/and delay. We investigated the challenges of providing an efficient open-source framework that benefits analytical and search-based approximation techniques simultaneously to both speed up the synthesis runtime and improve the quality of obtained results. Besides, we studied the utilization of machine learning algorithms to improve the performance of several critical steps, i.e., accelerator quality testing, in the synthesis framework. The proposed framework can help the community to rapidly generate efficient approximate accelerators in a reasonable runtime.","lang":"eng"}],"citation":{"mla":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, IEEE, 2021, pp. 384–89.","bibtex":"@inproceedings{Awais_Platzner_2021, title={MCTS-Based Synthesis Towards Efficient Approximate Accelerators}, booktitle={Proceedings of IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Awais, Muhammad and Platzner, Marco}, year={2021}, pages={384–389} }","ama":"Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators. In: <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>. IEEE; 2021:384-389.","ieee":"M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, Tampa, Florida USA (Virtual), 2021, pp. 384–389.","apa":"Awais, M., &#38; Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient Approximate Accelerators. <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, 384–389.","short":"M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, 2021, pp. 384–389.","chicago":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” In <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, 384–89. IEEE, 2021."},"publication":"Proceedings of IEEE Computer Society Annual Symposium on VLSI","department":[{"_id":"78"}],"type":"conference","keyword":["Approximate computing","Design space exploration","Accelerator synthesis"],"date_created":"2021-06-14T14:05:17Z"},{"year":"2021","status":"public","title":"Implementation and Profiling of XCS in the Context of Embedded Systems","author":[{"last_name":"Brede","first_name":"Mathis","full_name":"Brede, Mathis"}],"date_updated":"2022-01-06T06:55:33Z","_id":"22483","publisher":"Paderborn University","language":[{"iso":"eng"}],"user_id":"477","supervisor":[{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"full_name":"Hansmeier, Tim","first_name":"Tim","last_name":"Hansmeier","orcid":"0000-0003-1377-3339","id":"49992"}],"citation":{"mla":"Brede, Mathis. <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn University, 2021.","bibtex":"@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling of XCS in the Context of Embedded Systems}, publisher={Paderborn University}, author={Brede, Mathis}, year={2021} }","ama":"Brede M. <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University; 2021.","ieee":"M. Brede, <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University, 2021.","apa":"Brede, M. (2021). <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University.","short":"M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems, Paderborn University, Paderborn, 2021.","chicago":"Brede, Mathis. <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University, 2021."},"abstract":[{"text":"This bachelor thesis presents a C/C++ implementation of the XCS algorithm for an embedded system and profiling results concerning the execution time of the functions. These are then analyzed in relation to the input characteristics of the examined learning environments and compared with related work. Three main conclusions can be drawn from the measured results. First, the maximum size of the population of the classifiers influences the runtime of the genetic algorithm; second, the size of the input space has a direct effect on the execution time of the matching function; and last, a larger action space results in a longer runtime generating the prediction for the possible actions. The dependencies identified here can serve to optimize the computational efficiency and make XCS more suitable for embedded systems.","lang":"eng"}],"extern":"1","project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901","_id":"1"}],"place":"Paderborn","date_created":"2021-06-21T09:35:03Z","type":"bachelorsthesis","department":[{"_id":"78"}]},{"doi":"10.1007/978-3-030-79025-7_4","user_id":"3118","editor":[{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"full_name":"Derrien, Steven","last_name":"Derrien","first_name":"Steven"},{"full_name":"Diniz, Pedro","first_name":"Pedro","last_name":"Diniz"},{"last_name":"Chillet","first_name":"Daniel","full_name":"Chillet, Daniel"}],"publisher":"Springer Lecture Notes in Computer Science","_id":"21953","language":[{"iso":"eng"}],"series_title":"Reconfigurable Computing: Architectures, Tools, and Applications","date_updated":"2022-02-14T11:03:09Z","publication_status":"accepted","year":"2021","status":"public","title":"Timing Optimization for Virtual FPGA Configurations","conference":{"end_date":"2021-07-01","name":"International Symposium on Applied Reconfigurable Computing","start_date":"2021-06-29","location":"Virtual conference"},"author":[{"full_name":"Witschen, Linus Matthias","last_name":"Witschen","first_name":"Linus Matthias","id":"49051"},{"id":"3118","first_name":"Tobias","last_name":"Wiersema","full_name":"Wiersema, Tobias"},{"first_name":"Masood","last_name":"Raeisi Nafchi","full_name":"Raeisi Nafchi, Masood"},{"last_name":"Bockhorn","first_name":"Arne","full_name":"Bockhorn, Arne"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"type":"conference","department":[{"_id":"78"}],"date_created":"2021-05-04T14:18:46Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901 - Subproject B4","_id":"12"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication":"Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21)","citation":{"ama":"Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D, eds. <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>. Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science. doi:<a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>","bibtex":"@inproceedings{Witschen_Wiersema_Raeisi Nafchi_Bockhorn_Platzner, series={Reconfigurable Computing: Architectures, Tools, and Applications}, title={Timing Optimization for Virtual FPGA Configurations}, DOI={<a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>}, booktitle={Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)}, publisher={Springer Lecture Notes in Computer Science}, author={Witschen, Linus Matthias and Wiersema, Tobias and Raeisi Nafchi, Masood and Bockhorn, Arne and Platzner, Marco}, editor={Hannig, Frank and Derrien, Steven and Diniz, Pedro and Chillet, Daniel}, collection={Reconfigurable Computing: Architectures, Tools, and Applications} }","mla":"Witschen, Linus Matthias, et al. “Timing Optimization for Virtual FPGA Configurations.” <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>, edited by Frank Hannig et al., Springer Lecture Notes in Computer Science, doi:<a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Masood Raeisi Nafchi, Arne Bockhorn, and Marco Platzner. “Timing Optimization for Virtual FPGA Configurations.” In <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>, edited by Frank Hannig, Steven Derrien, Pedro Diniz, and Daniel Chillet. Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science, n.d. <a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">https://doi.org/10.1007/978-3-030-79025-7_4</a>.","short":"L.M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, M. Platzner, in: F. Hannig, S. Derrien, P. Diniz, D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Springer Lecture Notes in Computer Science, n.d.","apa":"Witschen, L. M., Wiersema, T., Raeisi Nafchi, M., Bockhorn, A., &#38; Platzner, M. (n.d.). Timing Optimization for Virtual FPGA Configurations. In F. Hannig, S. Derrien, P. Diniz, &#38; D. Chillet (Eds.), <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>. Springer Lecture Notes in Computer Science. <a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">https://doi.org/10.1007/978-3-030-79025-7_4</a>","ieee":"L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,” in <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>, Virtual conference, doi: <a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>."}},{"publication":"Journal of NeuroEngineering and Rehabilitation","issue":"1","abstract":[{"lang":"eng","text":"<jats:title>Abstract</jats:title><jats:sec>\r\n                <jats:title>Background</jats:title>\r\n                <jats:p>Hand amputation can have a truly debilitating impact on the life of the affected person. A multifunctional myoelectric prosthesis controlled using pattern classification can be used to restore some of the lost motor abilities. However, learning to control an advanced prosthesis can be a challenging task, but virtual and augmented reality (AR) provide means to create an engaging and motivating training.</jats:p>\r\n              </jats:sec><jats:sec>\r\n                <jats:title>Methods</jats:title>\r\n                <jats:p>In this study, we present a novel training framework that integrates virtual elements within a real scene (AR) while allowing the view from the first-person perspective. The framework was evaluated in 13 able-bodied subjects and a limb-deficient person divided into intervention (IG) and control (CG) groups. The IG received training by performing simulated clothespin task and both groups conducted a pre- and posttest with a real prosthesis. When training with the AR, the subjects received visual feedback on the generated grasping force. The main outcome measure was the number of pins that were successfully transferred within 20 min (task duration), while the number of dropped and broken pins were also registered. The participants were asked to score the difficulty of the real task (posttest), fun-factor and motivation, as well as the utility of the feedback.</jats:p>\r\n              </jats:sec><jats:sec>\r\n                <jats:title>Results</jats:title>\r\n                <jats:p>The performance (median/interquartile range) consistently increased during the training sessions (4/3 to 22/4). While the results were similar for the two groups in the pretest, the performance improved in the posttest only in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5 versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9) significantly fewer pins in the posttest compared to CG. The participants in IG assigned (mean ± std) significantly lower scores to the difficulty compared to CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3) and usefulness of feedback (8.5 ± 1.7).</jats:p>\r\n              </jats:sec><jats:sec>\r\n                <jats:title>Conclusion</jats:title>\r\n                <jats:p>The results demonstrated that the proposed AR system allows for the transfer of skills from the simulated to the real task while providing a positive user experience. The present study demonstrates the effectiveness and flexibility of the proposed AR framework. Importantly, the developed system is open source and available for download and further development.</jats:p>\r\n              </jats:sec>"}],"date_created":"2022-04-18T10:02:20Z","type":"journal_article","keyword":["Health Informatics","Rehabilitation"],"department":[{"_id":"78"}],"title":"Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis","year":"2021","publication_identifier":{"issn":["1743-0003"]},"author":[{"first_name":"Alexander","last_name":"Boschmann","full_name":"Boschmann, Alexander"},{"last_name":"Neuhaus","first_name":"Dorothee","full_name":"Neuhaus, Dorothee"},{"last_name":"Vogt","first_name":"Sarah","full_name":"Vogt, Sarah"},{"full_name":"Kaltschmidt, Christian","first_name":"Christian","last_name":"Kaltschmidt"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Dosen, Strahinja","last_name":"Dosen","first_name":"Strahinja"}],"publication_status":"published","date_updated":"2022-04-18T10:04:16Z","intvolume":"        18","article_number":"25","language":[{"iso":"eng"}],"doi":"10.1186/s12984-021-00822-6","citation":{"mla":"Boschmann, Alexander, et al. “Immersive Augmented Reality System for the Training of Pattern Classification Control with a Myoelectric Prosthesis.” <i>Journal of NeuroEngineering and Rehabilitation</i>, vol. 18, no. 1, 25, Springer Science and Business Media LLC, 2021, doi:<a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>.","bibtex":"@article{Boschmann_Neuhaus_Vogt_Kaltschmidt_Platzner_Dosen_2021, title={Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis}, volume={18}, DOI={<a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>}, number={125}, journal={Journal of NeuroEngineering and Rehabilitation}, publisher={Springer Science and Business Media LLC}, author={Boschmann, Alexander and Neuhaus, Dorothee and Vogt, Sarah and Kaltschmidt, Christian and Platzner, Marco and Dosen, Strahinja}, year={2021} }","ama":"Boschmann A, Neuhaus D, Vogt S, Kaltschmidt C, Platzner M, Dosen S. Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis. <i>Journal of NeuroEngineering and Rehabilitation</i>. 2021;18(1). doi:<a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>","ieee":"A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,” <i>Journal of NeuroEngineering and Rehabilitation</i>, vol. 18, no. 1, Art. no. 25, 2021, doi: <a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>.","apa":"Boschmann, A., Neuhaus, D., Vogt, S., Kaltschmidt, C., Platzner, M., &#38; Dosen, S. (2021). Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis. <i>Journal of NeuroEngineering and Rehabilitation</i>, <i>18</i>(1), Article 25. <a href=\"https://doi.org/10.1186/s12984-021-00822-6\">https://doi.org/10.1186/s12984-021-00822-6</a>","chicago":"Boschmann, Alexander, Dorothee Neuhaus, Sarah Vogt, Christian Kaltschmidt, Marco Platzner, and Strahinja Dosen. “Immersive Augmented Reality System for the Training of Pattern Classification Control with a Myoelectric Prosthesis.” <i>Journal of NeuroEngineering and Rehabilitation</i> 18, no. 1 (2021). <a href=\"https://doi.org/10.1186/s12984-021-00822-6\">https://doi.org/10.1186/s12984-021-00822-6</a>.","short":"A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, S. Dosen, Journal of NeuroEngineering and Rehabilitation 18 (2021)."},"status":"public","publisher":"Springer Science and Business Media LLC","_id":"30906","user_id":"398","volume":18}]