[{"abstract":[{"lang":"eng","text":"Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach."}],"status":"public","type":"journal_article","publication":"ACM Transactions on Reconfigurable Technology and Systems","language":[{"iso":"eng"}],"_id":"29150","user_id":"60323","department":[{"_id":"78"}],"year":"2021","citation":{"bibtex":"@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable Robotics Systems with ReconROS}, DOI={<a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Lienen, Christian and Platzner, Marco}, year={2021}, pages={1–20} }","mla":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2021, pp. 1–20, doi:<a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>.","short":"C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (2021) 1–20.","apa":"Lienen, C., &#38; Platzner, M. (2021). Design of Distributed Reconfigurable Robotics Systems with ReconROS. <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 1–20. <a href=\"https://doi.org/10.1145/3494571\">https://doi.org/10.1145/3494571</a>","chicago":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2021, 1–20. <a href=\"https://doi.org/10.1145/3494571\">https://doi.org/10.1145/3494571</a>.","ieee":"C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, pp. 1–20, 2021, doi: <a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>.","ama":"Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. Published online 2021:1-20. doi:<a href=\"https://doi.org/10.1145/3494571\">10.1145/3494571</a>"},"page":"1-20","publication_status":"published","publication_identifier":{"issn":["1936-7406","1936-7414"]},"title":"Design of Distributed Reconfigurable Robotics Systems with ReconROS","doi":"10.1145/3494571","date_updated":"2022-01-06T06:58:46Z","date_created":"2022-01-04T08:30:10Z","author":[{"last_name":"Lienen","id":"60323","full_name":"Lienen, Christian","first_name":"Christian"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}]},{"project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"1","name":"SFB 901"}],"_id":"29151","user_id":"49992","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"mastersthesis","abstract":[{"text":"Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique.","lang":"eng"}],"status":"public","publisher":"Paderborn University","date_updated":"2022-01-06T06:58:46Z","date_created":"2022-01-04T09:24:52Z","author":[{"first_name":"Chinmay","full_name":"Kashikar, Chinmay","last_name":"Kashikar"}],"supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"first_name":"Tim","last_name":"Hansmeier","orcid":"0000-0003-1377-3339","id":"49992","full_name":"Hansmeier, Tim"}],"title":"A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes","year":"2021","place":"Paderborn","citation":{"apa":"Kashikar, C. (2021). <i>A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn University.","bibtex":"@book{Kashikar_2021, place={Paderborn}, title={A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes}, publisher={Paderborn University}, author={Kashikar, Chinmay}, year={2021} }","short":"C. Kashikar, A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes, Paderborn University, Paderborn, 2021.","mla":"Kashikar, Chinmay. <i>A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn University, 2021.","chicago":"Kashikar, Chinmay. <i>A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn: Paderborn University, 2021.","ieee":"C. Kashikar, <i>A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn: Paderborn University, 2021.","ama":"Kashikar C. <i>A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn University; 2021."}},{"status":"public","type":"conference","publication":"Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021","language":[{"iso":"eng"}],"user_id":"64665","department":[{"_id":"78"}],"_id":"21610","citation":{"mla":"Awais, Muhammad, et al. “LDAX: A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.” <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>, ACM, 2021, pp. 27–32, doi:<a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>.","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32.","bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2021, title={LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis}, DOI={<a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>}, booktitle={Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2021}, pages={27–32} }","apa":"Awais, M., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2021). LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i> (pp. 27–32). Virtual: ACM. <a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In: <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>. ACM; 2021:27-32. doi:<a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>, Virtual, 2021, pp. 27–32.","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “LDAX: A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.” In <i>Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021</i>, 27–32. ACM, 2021. <a href=\"https://doi.org/10.1145/3453688.3461506\">https://doi.org/10.1145/3453688.3461506</a>."},"page":"27-32","year":"2021","publication_status":"published","doi":"https://doi.org/10.1145/3453688.3461506","conference":{"name":"31st ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021","start_date":"2021-06-22","end_date":"2021-06-25","location":"Virtual"},"title":"LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis","date_created":"2021-04-13T10:17:47Z","author":[{"first_name":"Muhammad","full_name":"Awais, Muhammad","id":"64665","orcid":"https://orcid.org/0000-0003-4148-2969","last_name":"Awais"},{"last_name":"Ghasemzadeh Mohammadi","id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"publisher":"ACM","date_updated":"2022-01-06T06:55:07Z"},{"year":"2021","citation":{"ama":"Rehnen JW. <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>.; 2021.","chicago":"Rehnen, Jakob Werner. <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>, 2021.","ieee":"J. W. Rehnen, <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>. 2021.","short":"J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib, 2021.","mla":"Rehnen, Jakob Werner. <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>. 2021.","bibtex":"@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner}, year={2021} }","apa":"Rehnen, J. W. (2021). <i>Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib</i>."},"date_updated":"2022-01-06T06:55:29Z","date_created":"2021-05-19T16:56:11Z","supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"first_name":"Linus Matthias","last_name":"Witschen","id":"49051","full_name":"Witschen, Linus Matthias"}],"author":[{"last_name":"Rehnen","full_name":"Rehnen, Jakob Werner","first_name":"Jakob Werner"}],"title":"Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib","type":"bachelorsthesis","status":"public","_id":"22216","department":[{"_id":"78"},{"_id":"7"}],"user_id":"49051","language":[{"iso":"eng"}]},{"publisher":"IEEE","date_updated":"2022-01-06T06:55:31Z","date_created":"2021-06-14T14:05:17Z","author":[{"full_name":"Awais, Muhammad","id":"64665","orcid":"https://orcid.org/0000-0003-4148-2969","last_name":"Awais","first_name":"Muhammad"},{"last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"title":"MCTS-Based Synthesis Towards Efficient Approximate Accelerators","conference":{"start_date":"2021-07-07","name":"IEEE Computer Society Annual Symposium on VLSI","location":"Tampa, Florida USA (Virtual)","end_date":"2021-07-09"},"year":"2021","page":"384-389","citation":{"ieee":"M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, Tampa, Florida USA (Virtual), 2021, pp. 384–389.","chicago":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” In <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, 384–89. IEEE, 2021.","ama":"Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators. In: <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>. IEEE; 2021:384-389.","short":"M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, 2021, pp. 384–389.","mla":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, IEEE, 2021, pp. 384–89.","bibtex":"@inproceedings{Awais_Platzner_2021, title={MCTS-Based Synthesis Towards Efficient Approximate Accelerators}, booktitle={Proceedings of IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Awais, Muhammad and Platzner, Marco}, year={2021}, pages={384–389} }","apa":"Awais, M., &#38; Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient Approximate Accelerators. <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, 384–389."},"_id":"22309","department":[{"_id":"78"}],"user_id":"64665","keyword":["Approximate computing","Design space exploration","Accelerator synthesis"],"language":[{"iso":"eng"}],"publication":"Proceedings of IEEE Computer Society Annual Symposium on VLSI","type":"conference","abstract":[{"text":"Approximate computing (AC) has acquired significant maturity in recent years as a promising approach to obtain energy and area-efficient hardware. Automated approximate accelerator synthesis involves a great deal of complexity on the size of design space which exponentially grows with the number of possible approximations. Design space exploration of approximate accelerator synthesis is usually targeted via heuristic-based search methods. The majority of existing frameworks prune a large part of the design space using a greedy-based approach to keep the problem tractable. Therefore, they result in inferior solutions since many potential solutions are neglected in the pruning process without the possibility of backtracking of removed approximate instances. In this paper, we address the aforementioned issue by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based search algorithm, in the context of automated synthesis of approximate accelerators. This enables the synthesis frameworks to deeply subsamples the design space of approximate accelerator synthesis toward most promising approximate instances based on the required performance goals, i.e., power consumption, area, or/and delay. We investigated the challenges of providing an efficient open-source framework that benefits analytical and search-based approximation techniques simultaneously to both speed up the synthesis runtime and improve the quality of obtained results. Besides, we studied the utilization of machine learning algorithms to improve the performance of several critical steps, i.e., accelerator quality testing, in the synthesis framework. The proposed framework can help the community to rapidly generate efficient approximate accelerators in a reasonable runtime.","lang":"eng"}],"status":"public"},{"user_id":"477","department":[{"_id":"78"}],"project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901","_id":"1"}],"_id":"22483","language":[{"iso":"eng"}],"extern":"1","type":"bachelorsthesis","status":"public","abstract":[{"text":"This bachelor thesis presents a C/C++ implementation of the XCS algorithm for an embedded system and profiling results concerning the execution time of the functions. These are then analyzed in relation to the input characteristics of the examined learning environments and compared with related work. Three main conclusions can be drawn from the measured results. First, the maximum size of the population of the classifiers influences the runtime of the genetic algorithm; second, the size of the input space has a direct effect on the execution time of the matching function; and last, a larger action space results in a longer runtime generating the prediction for the possible actions. The dependencies identified here can serve to optimize the computational efficiency and make XCS more suitable for embedded systems.","lang":"eng"}],"date_created":"2021-06-21T09:35:03Z","supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"first_name":"Tim","last_name":"Hansmeier","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","id":"49992"}],"author":[{"first_name":"Mathis","last_name":"Brede","full_name":"Brede, Mathis"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:55:33Z","title":"Implementation and Profiling of XCS in the Context of Embedded Systems","citation":{"ama":"Brede M. <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University; 2021.","ieee":"M. Brede, <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University, 2021.","chicago":"Brede, Mathis. <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University, 2021.","apa":"Brede, M. (2021). <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn: Paderborn University.","short":"M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems, Paderborn University, Paderborn, 2021.","bibtex":"@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling of XCS in the Context of Embedded Systems}, publisher={Paderborn University}, author={Brede, Mathis}, year={2021} }","mla":"Brede, Mathis. <i>Implementation and Profiling of XCS in the Context of Embedded Systems</i>. Paderborn University, 2021."},"year":"2021","place":"Paderborn"},{"language":[{"iso":"eng"}],"department":[{"_id":"78"}],"series_title":"Reconfigurable Computing: Architectures, Tools, and Applications","user_id":"3118","_id":"21953","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","editor":[{"first_name":"Frank","last_name":"Hannig","full_name":"Hannig, Frank"},{"last_name":"Derrien","full_name":"Derrien, Steven","first_name":"Steven"},{"first_name":"Pedro","full_name":"Diniz, Pedro","last_name":"Diniz"},{"first_name":"Daniel","last_name":"Chillet","full_name":"Chillet, Daniel"}],"publication":"Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21)","type":"conference","doi":"10.1007/978-3-030-79025-7_4","conference":{"name":"International Symposium on Applied Reconfigurable Computing","start_date":"2021-06-29","end_date":"2021-07-01","location":"Virtual conference"},"title":"Timing Optimization for Virtual FPGA Configurations","author":[{"id":"49051","full_name":"Witschen, Linus Matthias","last_name":"Witschen","first_name":"Linus Matthias"},{"last_name":"Wiersema","id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"last_name":"Raeisi Nafchi","full_name":"Raeisi Nafchi, Masood","first_name":"Masood"},{"first_name":"Arne","last_name":"Bockhorn","full_name":"Bockhorn, Arne"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2021-05-04T14:18:46Z","publisher":"Springer Lecture Notes in Computer Science","date_updated":"2022-02-14T11:03:09Z","citation":{"apa":"Witschen, L. M., Wiersema, T., Raeisi Nafchi, M., Bockhorn, A., &#38; Platzner, M. (n.d.). Timing Optimization for Virtual FPGA Configurations. In F. Hannig, S. Derrien, P. Diniz, &#38; D. Chillet (Eds.), <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>. Springer Lecture Notes in Computer Science. <a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">https://doi.org/10.1007/978-3-030-79025-7_4</a>","short":"L.M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, M. Platzner, in: F. Hannig, S. Derrien, P. Diniz, D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Springer Lecture Notes in Computer Science, n.d.","mla":"Witschen, Linus Matthias, et al. “Timing Optimization for Virtual FPGA Configurations.” <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>, edited by Frank Hannig et al., Springer Lecture Notes in Computer Science, doi:<a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>.","bibtex":"@inproceedings{Witschen_Wiersema_Raeisi Nafchi_Bockhorn_Platzner, series={Reconfigurable Computing: Architectures, Tools, and Applications}, title={Timing Optimization for Virtual FPGA Configurations}, DOI={<a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>}, booktitle={Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)}, publisher={Springer Lecture Notes in Computer Science}, author={Witschen, Linus Matthias and Wiersema, Tobias and Raeisi Nafchi, Masood and Bockhorn, Arne and Platzner, Marco}, editor={Hannig, Frank and Derrien, Steven and Diniz, Pedro and Chillet, Daniel}, collection={Reconfigurable Computing: Architectures, Tools, and Applications} }","ieee":"L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,” in <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>, Virtual conference, doi: <a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Masood Raeisi Nafchi, Arne Bockhorn, and Marco Platzner. “Timing Optimization for Virtual FPGA Configurations.” In <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>, edited by Frank Hannig, Steven Derrien, Pedro Diniz, and Daniel Chillet. Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science, n.d. <a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">https://doi.org/10.1007/978-3-030-79025-7_4</a>.","ama":"Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D, eds. <i>Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)</i>. Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science. doi:<a href=\"https://doi.org/10.1007/978-3-030-79025-7_4\">10.1007/978-3-030-79025-7_4</a>"},"year":"2021","publication_status":"accepted"},{"doi":"10.1186/s12984-021-00822-6","title":"Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis","date_created":"2022-04-18T10:02:20Z","author":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"},{"full_name":"Neuhaus, Dorothee","last_name":"Neuhaus","first_name":"Dorothee"},{"first_name":"Sarah","last_name":"Vogt","full_name":"Vogt, Sarah"},{"first_name":"Christian","last_name":"Kaltschmidt","full_name":"Kaltschmidt, Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Strahinja","last_name":"Dosen","full_name":"Dosen, Strahinja"}],"volume":18,"date_updated":"2022-04-18T10:04:16Z","publisher":"Springer Science and Business Media LLC","citation":{"apa":"Boschmann, A., Neuhaus, D., Vogt, S., Kaltschmidt, C., Platzner, M., &#38; Dosen, S. (2021). Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis. <i>Journal of NeuroEngineering and Rehabilitation</i>, <i>18</i>(1), Article 25. <a href=\"https://doi.org/10.1186/s12984-021-00822-6\">https://doi.org/10.1186/s12984-021-00822-6</a>","short":"A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, S. Dosen, Journal of NeuroEngineering and Rehabilitation 18 (2021).","mla":"Boschmann, Alexander, et al. “Immersive Augmented Reality System for the Training of Pattern Classification Control with a Myoelectric Prosthesis.” <i>Journal of NeuroEngineering and Rehabilitation</i>, vol. 18, no. 1, 25, Springer Science and Business Media LLC, 2021, doi:<a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>.","bibtex":"@article{Boschmann_Neuhaus_Vogt_Kaltschmidt_Platzner_Dosen_2021, title={Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis}, volume={18}, DOI={<a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>}, number={125}, journal={Journal of NeuroEngineering and Rehabilitation}, publisher={Springer Science and Business Media LLC}, author={Boschmann, Alexander and Neuhaus, Dorothee and Vogt, Sarah and Kaltschmidt, Christian and Platzner, Marco and Dosen, Strahinja}, year={2021} }","ama":"Boschmann A, Neuhaus D, Vogt S, Kaltschmidt C, Platzner M, Dosen S. Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis. <i>Journal of NeuroEngineering and Rehabilitation</i>. 2021;18(1). doi:<a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>","chicago":"Boschmann, Alexander, Dorothee Neuhaus, Sarah Vogt, Christian Kaltschmidt, Marco Platzner, and Strahinja Dosen. “Immersive Augmented Reality System for the Training of Pattern Classification Control with a Myoelectric Prosthesis.” <i>Journal of NeuroEngineering and Rehabilitation</i> 18, no. 1 (2021). <a href=\"https://doi.org/10.1186/s12984-021-00822-6\">https://doi.org/10.1186/s12984-021-00822-6</a>.","ieee":"A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,” <i>Journal of NeuroEngineering and Rehabilitation</i>, vol. 18, no. 1, Art. no. 25, 2021, doi: <a href=\"https://doi.org/10.1186/s12984-021-00822-6\">10.1186/s12984-021-00822-6</a>."},"intvolume":"        18","year":"2021","issue":"1","publication_status":"published","publication_identifier":{"issn":["1743-0003"]},"language":[{"iso":"eng"}],"article_number":"25","keyword":["Health Informatics","Rehabilitation"],"user_id":"398","department":[{"_id":"78"}],"_id":"30906","status":"public","abstract":[{"text":"<jats:title>Abstract</jats:title><jats:sec>\r\n                <jats:title>Background</jats:title>\r\n                <jats:p>Hand amputation can have a truly debilitating impact on the life of the affected person. A multifunctional myoelectric prosthesis controlled using pattern classification can be used to restore some of the lost motor abilities. However, learning to control an advanced prosthesis can be a challenging task, but virtual and augmented reality (AR) provide means to create an engaging and motivating training.</jats:p>\r\n              </jats:sec><jats:sec>\r\n                <jats:title>Methods</jats:title>\r\n                <jats:p>In this study, we present a novel training framework that integrates virtual elements within a real scene (AR) while allowing the view from the first-person perspective. The framework was evaluated in 13 able-bodied subjects and a limb-deficient person divided into intervention (IG) and control (CG) groups. The IG received training by performing simulated clothespin task and both groups conducted a pre- and posttest with a real prosthesis. When training with the AR, the subjects received visual feedback on the generated grasping force. The main outcome measure was the number of pins that were successfully transferred within 20 min (task duration), while the number of dropped and broken pins were also registered. The participants were asked to score the difficulty of the real task (posttest), fun-factor and motivation, as well as the utility of the feedback.</jats:p>\r\n              </jats:sec><jats:sec>\r\n                <jats:title>Results</jats:title>\r\n                <jats:p>The performance (median/interquartile range) consistently increased during the training sessions (4/3 to 22/4). While the results were similar for the two groups in the pretest, the performance improved in the posttest only in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5 versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9) significantly fewer pins in the posttest compared to CG. The participants in IG assigned (mean ± std) significantly lower scores to the difficulty compared to CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3) and usefulness of feedback (8.5 ± 1.7).</jats:p>\r\n              </jats:sec><jats:sec>\r\n                <jats:title>Conclusion</jats:title>\r\n                <jats:p>The results demonstrated that the proposed AR system allows for the transfer of skills from the simulated to the real task while providing a positive user experience. The present study demonstrates the effectiveness and flexibility of the proposed AR framework. Importantly, the developed system is open source and available for download and further development.</jats:p>\r\n              </jats:sec>","lang":"eng"}],"type":"journal_article","publication":"Journal of NeuroEngineering and Rehabilitation"},{"doi":"10.1109/tc.2021.3107196","title":"Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs","author":[{"last_name":"Rodriguez","full_name":"Rodriguez, Alfonso","first_name":"Alfonso"},{"last_name":"Otero","full_name":"Otero, Andres","first_name":"Andres"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"De la Torre, Eduardo","last_name":"De la Torre","first_name":"Eduardo"}],"date_created":"2022-04-18T10:03:16Z","date_updated":"2022-04-18T10:04:21Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","citation":{"ama":"Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>. Published online 2021:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>","ieee":"A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","chicago":"Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, 2021, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>.","apa":"Rodriguez, A., Otero, A., Platzner, M., &#38; De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>","mla":"Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","bibtex":"@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }","short":"A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1."},"page":"1-1","year":"2021","publication_status":"published","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"language":[{"iso":"eng"}],"keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"user_id":"398","department":[{"_id":"78"}],"_id":"30907","status":"public","type":"journal_article","publication":"IEEE Transactions on Computers"},{"language":[{"iso":"eng"}],"project":[{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901: SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"_id":"29137","user_id":"477","department":[{"_id":"78"}],"status":"public","type":"conference","publication":"HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","title":"Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS","conference":{"location":"Online","end_date":"2021-06-23","start_date":"2021-06-21","name":"International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21)"},"doi":"10.1145/3468044.3468055","date_updated":"2022-11-18T10:03:24Z","publisher":"Association for Computing Machinery (ACM)","author":[{"first_name":"Tim","full_name":"Hansmeier, Tim","id":"49992","last_name":"Hansmeier","orcid":"0000-0003-1377-3339"}],"date_created":"2021-12-27T12:01:02Z","place":"New York, NY, United States","year":"2021","citation":{"ieee":"T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,” presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi: <a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>.","chicago":"Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using the Learning Classifier System XCS.” In <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. New York, NY, United States: Association for Computing Machinery (ACM), 2021. <a href=\"https://doi.org/10.1145/3468044.3468055\">https://doi.org/10.1145/3468044.3468055</a>.","ama":"Hansmeier T. Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. In: <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. Association for Computing Machinery (ACM); 2021. doi:<a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>","short":"T. Hansmeier, in: HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Association for Computing Machinery (ACM), New York, NY, United States, 2021.","bibtex":"@inproceedings{Hansmeier_2021, place={New York, NY, United States}, title={Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS}, DOI={<a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>}, booktitle={HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim}, year={2021} }","mla":"Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using the Learning Classifier System XCS.” <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>, Association for Computing Machinery (ACM), 2021, doi:<a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>.","apa":"Hansmeier, T. (2021). Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online. <a href=\"https://doi.org/10.1145/3468044.3468055\">https://doi.org/10.1145/3468044.3468055</a>"},"publication_status":"published"},{"status":"public","abstract":[{"text":"Autonomous mobile robots are becoming increasingly more capable and widespread. Reliable Obstacle avoidance is an integral part of autonomous navigation. This involves real time interpretation and processing of a complex environment. Strict time and energy constraints of a mobile autonomous system make efficient computation extremely desirable. The benefits of employing Hardware/Software co-designed applications are obvious and significant. Hardware accelerators are used for efficient processing of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators, which\r\ncan contain hundreds of small execution units, and can be used for Hardware/Software co-designed application. However, there is a reluctance when it comes to adoption of these devices in well established application domains, such as Robotics, due to a steep learning curve needed for FPGA application design. ReconROS has successfully bridged the gap between robotic and FPGA application development, by providing an intuitive, common development platform for robotic application development for FPGA. It does so by integrating Robotics Operating System(ROS) which is an industry and academia standard for robotics application development, with ReconOS, an operating system for re-configurable hardware. In this thesis an obstacle avoidance system is designed and implemented for an autonomous vehicle using ReconROS. The objectives of the thesis is to demonstrate and explore ReconROS integration within the ROS ecosystem and explore the design process within ReconROS framework, and to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing the resulting architectures for Latency and Power Consumption.","lang":"eng"}],"type":"mastersthesis","language":[{"iso":"eng"}],"user_id":"60323","department":[{"_id":"78"}],"_id":"29540","citation":{"chicago":"Sheikh, Muhammad Aamir. <i>Design and Implementation of a ReconROS-Based Obstacle Avoidance System</i>. Paderborn University, 2021.","ieee":"M. A. Sheikh, <i>Design and Implementation of a ReconROS-based Obstacle Avoidance System</i>. Paderborn University, 2021.","ama":"Sheikh MA. <i>Design and Implementation of a ReconROS-Based Obstacle Avoidance System</i>. Paderborn University; 2021.","apa":"Sheikh, M. A. (2021). <i>Design and Implementation of a ReconROS-based Obstacle Avoidance System</i>. Paderborn University.","bibtex":"@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh, Muhammad Aamir}, year={2021} }","short":"M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance System, Paderborn University, 2021.","mla":"Sheikh, Muhammad Aamir. <i>Design and Implementation of a ReconROS-Based Obstacle Avoidance System</i>. Paderborn University, 2021."},"year":"2021","title":"Design and Implementation of a ReconROS-based Obstacle Avoidance System","supervisor":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Christian","last_name":"Lienen","full_name":"Lienen, Christian","id":"60323"}],"date_created":"2022-01-26T08:50:52Z","author":[{"last_name":"Sheikh","full_name":"Sheikh, Muhammad Aamir","first_name":"Muhammad Aamir"}],"date_updated":"2022-01-28T08:30:46Z","publisher":"Paderborn University"},{"language":[{"iso":"eng"}],"_id":"22764","user_id":"60323","department":[{"_id":"78"}],"abstract":[{"lang":"eng","text":"Robotics applications process large amounts of data in real-time and require compute platforms that provide high performance and energy-efficiency. FPGAs are well-suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this paper we present ReconROS, a framework that integrates the widely-used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach."}],"status":"public","type":"preprint","publication":"arXiv:2107.07208","title":"Design of Distributed Reconfigurable Robotics Systems with ReconROS","main_file_link":[{"open_access":"1","url":"https://arxiv.org/abs/2107.07208"}],"oa":"1","date_updated":"2022-01-28T08:30:24Z","author":[{"first_name":"Christian","id":"60323","full_name":"Lienen, Christian","last_name":"Lienen"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2021-07-16T05:38:56Z","year":"2021","citation":{"apa":"Lienen, C., &#38; Platzner, M. (2021). Design of Distributed Reconfigurable Robotics Systems with ReconROS. In <i>arXiv:2107.07208</i>.","short":"C. Lienen, M. Platzner, ArXiv:2107.07208 (2021).","bibtex":"@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable Robotics Systems with ReconROS}, journal={arXiv:2107.07208}, author={Lienen, Christian and Platzner, Marco}, year={2021} }","mla":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ArXiv:2107.07208</i>, 2021.","ama":"Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. <i>arXiv:210707208</i>. Published online 2021.","ieee":"C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” <i>arXiv:2107.07208</i>. 2021.","chicago":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ArXiv:2107.07208</i>, 2021."},"page":"19"},{"year":"2021","place":"New York, NY, United States","citation":{"apa":"Hansmeier, T., &#38; Platzner, M. (2021). An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS. <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 1639–1647. <a href=\"https://doi.org/10.1145/3449726.3463159\">https://doi.org/10.1145/3449726.3463159</a>","short":"T. Hansmeier, M. Platzner, in: GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2021, pp. 1639–1647.","mla":"Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS.” <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Association for Computing Machinery (ACM), 2021, pp. 1639–1647, doi:<a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>.","bibtex":"@inproceedings{Hansmeier_Platzner_2021, place={New York, NY, United States}, title={An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS}, DOI={<a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>}, booktitle={GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Platzner, Marco}, year={2021}, pages={1639–1647} }","ama":"Hansmeier T, Platzner M. An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS. In: <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>. Association for Computing Machinery (ACM); 2021:1639–1647. doi:<a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>","chicago":"Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS.” In <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 1639–1647. New York, NY, United States: Association for Computing Machinery (ACM), 2021. <a href=\"https://doi.org/10.1145/3449726.3463159\">https://doi.org/10.1145/3449726.3463159</a>.","ieee":"T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,” in <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Lille, France, 2021, pp. 1639–1647, doi: <a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>."},"page":"1639–1647","publication_status":"published","publication_identifier":{"isbn":["978-1-4503-8351-6"]},"title":"An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS","doi":"10.1145/3449726.3463159","conference":{"start_date":"2021-07-10","name":"International Workshop on Learning Classifier Systems (IWLCS 2021)","location":"Lille, France","end_date":"2021-07-14"},"date_updated":"2022-09-02T09:42:38Z","publisher":"Association for Computing Machinery (ACM)","author":[{"orcid":"0000-0003-1377-3339","last_name":"Hansmeier","full_name":"Hansmeier, Tim","id":"49992","first_name":"Tim"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2021-04-28T09:08:17Z","status":"public","type":"conference","publication":"GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion","language":[{"iso":"eng"}],"project":[{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"_id":"21813","user_id":"49992","department":[{"_id":"78"}]},{"type":"journal_article","publication":"IEEE Access","abstract":[{"text":"Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.","lang":"eng"}],"status":"public","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - Subproject B4"}],"_id":"27841","user_id":"22398","department":[{"_id":"78"}],"keyword":["Software Analysis","Abstract Interpretation","Custom Instruction","Hardware Verification"],"language":[{"iso":"eng"}],"funded_apc":"1","publication_status":"published","quality_controlled":"1","year":"2021","citation":{"mla":"Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” <i>IEEE Access</i>, IEEE, 2021, doi:<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>.","bibtex":"@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware Co-Verification for Custom Instruction Set Processors}, DOI={<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>}, journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021} }","short":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021).","apa":"Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., &#38; Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. <i>IEEE Access</i>. <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">https://doi.org/10.1109/ACCESS.2021.3131213</a>","ama":"Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. <i>IEEE Access</i>. Published online 2021. doi:<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>","ieee":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” <i>IEEE Access</i>, 2021, doi: <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>.","chicago":"Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” <i>IEEE Access</i>, 2021. <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">https://doi.org/10.1109/ACCESS.2021.3131213</a>."},"publisher":"IEEE","date_updated":"2023-01-18T08:34:50Z","author":[{"full_name":"Jakobs, Marie-Christine","last_name":"Jakobs","first_name":"Marie-Christine"},{"first_name":"Felix","last_name":"Pauck","id":"22398","full_name":"Pauck, Felix"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"},{"first_name":"Heike","last_name":"Wehrheim","id":"573","full_name":"Wehrheim, Heike"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","id":"3118","last_name":"Wiersema"}],"date_created":"2021-11-25T14:12:22Z","title":"Software/Hardware Co-Verification for Custom Instruction Set Processors","doi":"10.1109/ACCESS.2021.3131213"},{"year":"2021","citation":{"ama":"Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>. ; 2021. doi:<a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>","ieee":"Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: <a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>.","chicago":"Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” In <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2021. <a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">https://doi.org/10.1109/vlsi-soc53125.2021.9606974</a>.","apa":"Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>. <a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">https://doi.org/10.1109/vlsi-soc53125.2021.9606974</a>","short":"Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021.","bibtex":"@inproceedings{Ahmed_2021, title={Hardware Trojans in Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>}, booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Ahmed, Qazi Arbab}, year={2021} }","mla":"Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2021, doi:<a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>."},"publication_status":"published","title":"Hardware Trojans in Reconfigurable Computing","doi":"10.1109/vlsi-soc53125.2021.9606974","date_updated":"2023-04-19T15:03:45Z","author":[{"id":"72764","full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed","orcid":"0000-0002-1837-2254","first_name":"Qazi Arbab"}],"date_created":"2021-12-30T00:02:24Z","status":"public","type":"conference","publication":"2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)","language":[{"iso":"eng"}],"project":[{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"},{"name":"SFB 901: SFB 901","_id":"1"}],"_id":"29138","user_id":"72764","department":[{"_id":"78"}]},{"year":"2021","publisher":"2021 Design, Automation and Test in Europe Conference (DATE)","date_created":"2020-12-07T14:03:00Z","title":"Malicious Routing: Circumventing Bitstream-level Verification for FPGAs","publication":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","abstract":[{"lang":"eng","text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques."}],"file":[{"file_id":"44752","access_level":"closed","file_name":"1812.pdf","file_size":394011,"creator":"qazi","date_created":"2023-05-11T09:16:15Z","date_updated":"2023-05-11T09:16:15Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"ddc":["006"],"language":[{"iso":"eng"}],"has_accepted_license":"1","publication_identifier":{"eisbn":["978-3-9819263-5-4"]},"publication_status":"published","place":"Alpexpo | Grenoble, France","citation":{"apa":"Ahmed, Q. A., Wiersema, T., &#38; Platzner, M. (2021). Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. <a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">https://doi.org/10.23919/DATE51398.2021.9474026</a>","short":"Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.","mla":"Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 2021 Design, Automation and Test in Europe Conference (DATE), 2021, doi:<a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>.","bibtex":"@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble, France}, title={Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}, DOI={<a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>}, booktitle={2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021} }","chicago":"Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” In <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. Alpexpo | Grenoble, France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. <a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">https://doi.org/10.23919/DATE51398.2021.9474026</a>.","ieee":"Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: <a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>.","ama":"Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. 2021 Design, Automation and Test in Europe Conference (DATE); 2021. doi:<a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>"},"oa":"1","date_updated":"2023-05-11T09:16:34Z","author":[{"id":"72764","full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed","orcid":"0000-0002-1837-2254","first_name":"Qazi Arbab"},{"last_name":"Wiersema","id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"doi":"10.23919/DATE51398.2021.9474026","conference":{"start_date":"2021-02-01","name":"Design, Automation and Test in Europe Conference (DATE'21)","location":"Alpexpo | Grenoble, France","end_date":"2021-02-05"},"main_file_link":[{"open_access":"1"}],"type":"conference","status":"public","_id":"20681","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901","_id":"1"}],"department":[{"_id":"78"}],"user_id":"72764","file_date_updated":"2023-05-11T09:16:15Z"},{"user_id":"398","department":[{"_id":"78"}],"project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1","grant_number":"160364472"}],"_id":"30909","language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","status":"public","date_created":"2022-04-18T10:17:47Z","author":[{"first_name":"Lennart","full_name":"Clausing, Lennart","id":"74287","orcid":"0000-0003-3789-6034","last_name":"Clausing"}],"date_updated":"2023-07-09T13:09:11Z","publisher":"ACM","doi":"10.1145/3468044.3468056","title":"ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip","publication_status":"published","citation":{"apa":"Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. <a href=\"https://doi.org/10.1145/3468044.3468056\">https://doi.org/10.1145/3468044.3468056</a>","bibtex":"@inproceedings{Clausing_2021, title={ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip}, DOI={<a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>}, booktitle={Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={ACM}, author={Clausing, Lennart}, year={2021} }","mla":"Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip.” <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>, ACM, 2021, doi:<a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>.","short":"L. Clausing, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2021.","ama":"Clausing L. ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. In: <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. ACM; 2021. doi:<a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>","chicago":"Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip.” In <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. ACM, 2021. <a href=\"https://doi.org/10.1145/3468044.3468056\">https://doi.org/10.1145/3468044.3468056</a>.","ieee":"L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,” 2021, doi: <a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>."},"year":"2021"},{"project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"},{"_id":"82","name":"SFB 901 - T: SFB 901 - Project Area T"}],"_id":"30908","user_id":"477","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"conference","publication":" Machine Learning and Principles and Practice of Knowledge Discovery in Databases","status":"public","publisher":"Springer","date_updated":"2023-09-15T15:09:07Z","date_created":"2022-04-18T10:16:55Z","author":[{"id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan"},{"first_name":"Felix","orcid":"0000-0003-4987-5708","last_name":"Jentzsch","full_name":"Jentzsch, Felix","id":"55631"},{"full_name":"Kuschel, Maurice","last_name":"Kuschel","first_name":"Maurice"},{"first_name":"Rahil ","full_name":"Arshad, Rahil ","last_name":"Arshad"},{"full_name":"Rautmare, Sneha","last_name":"Rautmare","first_name":"Sneha"},{"full_name":"Manjunatha, Suraj","last_name":"Manjunatha","first_name":"Suraj"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Alexander","last_name":"Boschmann","full_name":"Boschmann, Alexander"},{"first_name":"Dirk ","last_name":"Schollbach","full_name":"Schollbach, Dirk "}],"title":"FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics","doi":"https://doi.org/10.1007/978-3-030-93736-2_27","year":"2021","citation":{"ieee":"H. Ghasemzadeh Mohammadi <i>et al.</i>, “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,” 2021, doi: <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>.","chicago":"Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil  Arshad, Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk  Schollbach. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” In <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. Springer, 2021. <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>.","ama":"Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. In: <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. Springer; 2021. doi:<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>","apa":"Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare, S., Manjunatha, S., Platzner, M., Boschmann, A., &#38; Schollbach, D. (2021). FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021, title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics}, DOI={<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>}, booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil  and Rautmare, Sneha and Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk }, year={2021} }","short":"H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare, S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in:  Machine Learning and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>, Springer, 2021, doi:<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>."}},{"publication":"Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)","type":"conference","status":"public","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"user_id":"398","_id":"3583","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{ Guetttatfi_Kaufmann_Platzner_2020, title={Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices}, booktitle={Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}, author={ Guetttatfi, Zakarya and Kaufmann, Paul and Platzner, Marco}, year={2020} }","short":"Z.  Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.","mla":"Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2020.","apa":"Guetttatfi, Z., Kaufmann, P., &#38; Platzner, M. (2020). Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>.","ama":"Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In: <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. ; 2020.","ieee":"Z.  Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2020.","chicago":"Guetttatfi, Zakarya, Paul Kaufmann, and Marco Platzner. “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2020."},"year":"2020","date_created":"2018-07-20T14:07:15Z","author":[{"full_name":" Guetttatfi, Zakarya","last_name":" Guetttatfi","first_name":"Zakarya"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-01-06T06:59:25Z","title":"Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices"},{"citation":{"short":"K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis, 2020.","mla":"Chandrakar, Khushboo. <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>. 2020.","bibtex":"@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020} }","apa":"Chandrakar, K. (2020). <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>.","ieee":"K. Chandrakar, <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>. 2020.","chicago":"Chandrakar, Khushboo. <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>, 2020.","ama":"Chandrakar K. <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>.; 2020."},"year":"2020","author":[{"full_name":"Chandrakar, Khushboo","last_name":"Chandrakar","first_name":"Khushboo"}],"supervisor":[{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"},{"last_name":"Witschen","id":"49051","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"}],"date_created":"2021-03-01T09:19:29Z","date_updated":"2022-01-06T06:54:54Z","title":"Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis","type":"mastersthesis","status":"public","user_id":"49051","department":[{"_id":"78"},{"_id":"7"}],"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"21324","language":[{"iso":"eng"}]}]