[{"date_created":"2022-04-18T10:03:16Z","type":"journal_article","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"department":[{"_id":"78"}],"publication":"IEEE Transactions on Computers","citation":{"apa":"Rodriguez, A., Otero, A., Platzner, M., &#38; De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>","ieee":"A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","short":"A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1.","chicago":"Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, 2021, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>.","mla":"Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","ama":"Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>. Published online 2021:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>","bibtex":"@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }"},"page":"1-1","_id":"30907","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","language":[{"iso":"eng"}],"user_id":"398","doi":"10.1109/tc.2021.3107196","status":"public","year":"2021","title":"Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"author":[{"full_name":"Rodriguez, Alfonso","last_name":"Rodriguez","first_name":"Alfonso"},{"full_name":"Otero, Andres","first_name":"Andres","last_name":"Otero"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"last_name":"De la Torre","first_name":"Eduardo","full_name":"De la Torre, Eduardo"}],"publication_status":"published","date_updated":"2022-04-18T10:04:21Z"},{"date_created":"2021-12-27T12:01:02Z","place":"New York, NY, United States","type":"conference","department":[{"_id":"78"}],"publication":"HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","citation":{"mla":"Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using the Learning Classifier System XCS.” <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>, Association for Computing Machinery (ACM), 2021, doi:<a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>.","ama":"Hansmeier T. Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. In: <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. Association for Computing Machinery (ACM); 2021. doi:<a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>","bibtex":"@inproceedings{Hansmeier_2021, place={New York, NY, United States}, title={Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS}, DOI={<a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>}, booktitle={HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim}, year={2021} }","apa":"Hansmeier, T. (2021). Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online. <a href=\"https://doi.org/10.1145/3468044.3468055\">https://doi.org/10.1145/3468044.3468055</a>","ieee":"T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,” presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi: <a href=\"https://doi.org/10.1145/3468044.3468055\">10.1145/3468044.3468055</a>.","chicago":"Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using the Learning Classifier System XCS.” In <i>HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. New York, NY, United States: Association for Computing Machinery (ACM), 2021. <a href=\"https://doi.org/10.1145/3468044.3468055\">https://doi.org/10.1145/3468044.3468055</a>.","short":"T. Hansmeier, in: HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Association for Computing Machinery (ACM), New York, NY, United States, 2021."},"project":[{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901: SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"_id":"29137","language":[{"iso":"eng"}],"publisher":"Association for Computing Machinery (ACM)","user_id":"477","doi":"10.1145/3468044.3468055","year":"2021","title":"Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS","status":"public","author":[{"first_name":"Tim","last_name":"Hansmeier","orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","id":"49992"}],"conference":{"end_date":"2021-06-23","location":"Online","start_date":"2021-06-21","name":"International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21)"},"publication_status":"published","date_updated":"2022-11-18T10:03:24Z"},{"abstract":[{"text":"Autonomous mobile robots are becoming increasingly more capable and widespread. Reliable Obstacle avoidance is an integral part of autonomous navigation. This involves real time interpretation and processing of a complex environment. Strict time and energy constraints of a mobile autonomous system make efficient computation extremely desirable. The benefits of employing Hardware/Software co-designed applications are obvious and significant. Hardware accelerators are used for efficient processing of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators, which\r\ncan contain hundreds of small execution units, and can be used for Hardware/Software co-designed application. However, there is a reluctance when it comes to adoption of these devices in well established application domains, such as Robotics, due to a steep learning curve needed for FPGA application design. ReconROS has successfully bridged the gap between robotic and FPGA application development, by providing an intuitive, common development platform for robotic application development for FPGA. It does so by integrating Robotics Operating System(ROS) which is an industry and academia standard for robotics application development, with ReconOS, an operating system for re-configurable hardware. In this thesis an obstacle avoidance system is designed and implemented for an autonomous vehicle using ReconROS. The objectives of the thesis is to demonstrate and explore ReconROS integration within the ROS ecosystem and explore the design process within ReconROS framework, and to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing the resulting architectures for Latency and Power Consumption.","lang":"eng"}],"supervisor":[{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Lienen, Christian","last_name":"Lienen","first_name":"Christian","id":"60323"}],"citation":{"mla":"Sheikh, Muhammad Aamir. <i>Design and Implementation of a ReconROS-Based Obstacle Avoidance System</i>. Paderborn University, 2021.","ama":"Sheikh MA. <i>Design and Implementation of a ReconROS-Based Obstacle Avoidance System</i>. Paderborn University; 2021.","bibtex":"@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh, Muhammad Aamir}, year={2021} }","apa":"Sheikh, M. A. (2021). <i>Design and Implementation of a ReconROS-based Obstacle Avoidance System</i>. Paderborn University.","ieee":"M. A. Sheikh, <i>Design and Implementation of a ReconROS-based Obstacle Avoidance System</i>. Paderborn University, 2021.","chicago":"Sheikh, Muhammad Aamir. <i>Design and Implementation of a ReconROS-Based Obstacle Avoidance System</i>. Paderborn University, 2021.","short":"M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance System, Paderborn University, 2021."},"type":"mastersthesis","department":[{"_id":"78"}],"date_created":"2022-01-26T08:50:52Z","date_updated":"2022-01-28T08:30:46Z","title":"Design and Implementation of a ReconROS-based Obstacle Avoidance System","status":"public","year":"2021","author":[{"full_name":"Sheikh, Muhammad Aamir","first_name":"Muhammad Aamir","last_name":"Sheikh"}],"user_id":"60323","_id":"29540","publisher":"Paderborn University","language":[{"iso":"eng"}]},{"main_file_link":[{"url":"https://arxiv.org/abs/2107.07208","open_access":"1"}],"page":"19","_id":"22764","language":[{"iso":"eng"}],"user_id":"60323","status":"public","title":"Design of Distributed Reconfigurable Robotics Systems with ReconROS","year":"2021","author":[{"last_name":"Lienen","first_name":"Christian","full_name":"Lienen, Christian","id":"60323"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"date_updated":"2022-01-28T08:30:24Z","date_created":"2021-07-16T05:38:56Z","type":"preprint","oa":"1","department":[{"_id":"78"}],"publication":"arXiv:2107.07208","citation":{"short":"C. Lienen, M. Platzner, ArXiv:2107.07208 (2021).","chicago":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ArXiv:2107.07208</i>, 2021.","apa":"Lienen, C., &#38; Platzner, M. (2021). Design of Distributed Reconfigurable Robotics Systems with ReconROS. In <i>arXiv:2107.07208</i>.","ieee":"C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” <i>arXiv:2107.07208</i>. 2021.","ama":"Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. <i>arXiv:210707208</i>. Published online 2021.","bibtex":"@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable Robotics Systems with ReconROS}, journal={arXiv:2107.07208}, author={Lienen, Christian and Platzner, Marco}, year={2021} }","mla":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” <i>ArXiv:2107.07208</i>, 2021."},"abstract":[{"text":"Robotics applications process large amounts of data in real-time and require compute platforms that provide high performance and energy-efficiency. FPGAs are well-suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this paper we present ReconROS, a framework that integrates the widely-used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.","lang":"eng"}]},{"citation":{"apa":"Hansmeier, T., &#38; Platzner, M. (2021). An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS. <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 1639–1647. <a href=\"https://doi.org/10.1145/3449726.3463159\">https://doi.org/10.1145/3449726.3463159</a>","ieee":"T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,” in <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Lille, France, 2021, pp. 1639–1647, doi: <a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>.","chicago":"Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS.” In <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, 1639–1647. New York, NY, United States: Association for Computing Machinery (ACM), 2021. <a href=\"https://doi.org/10.1145/3449726.3463159\">https://doi.org/10.1145/3449726.3463159</a>.","short":"T. Hansmeier, M. Platzner, in: GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2021, pp. 1639–1647.","mla":"Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS.” <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>, Association for Computing Machinery (ACM), 2021, pp. 1639–1647, doi:<a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>.","ama":"Hansmeier T, Platzner M. An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS. In: <i>GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion</i>. Association for Computing Machinery (ACM); 2021:1639–1647. doi:<a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>","bibtex":"@inproceedings{Hansmeier_Platzner_2021, place={New York, NY, United States}, title={An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS}, DOI={<a href=\"https://doi.org/10.1145/3449726.3463159\">10.1145/3449726.3463159</a>}, booktitle={GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Platzner, Marco}, year={2021}, pages={1639–1647} }"},"project":[{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"place":"New York, NY, United States","status":"public","conference":{"location":"Lille, France","start_date":"2021-07-10","name":"International Workshop on Learning Classifier Systems (IWLCS 2021)","end_date":"2021-07-14"},"page":"1639–1647","publisher":"Association for Computing Machinery (ACM)","_id":"21813","user_id":"49992","publication":"GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion","date_created":"2021-04-28T09:08:17Z","type":"conference","department":[{"_id":"78"}],"year":"2021","title":"An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS","author":[{"id":"49992","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","last_name":"Hansmeier","first_name":"Tim"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"publication_identifier":{"isbn":["978-1-4503-8351-6"]},"publication_status":"published","date_updated":"2022-09-02T09:42:38Z","language":[{"iso":"eng"}],"doi":"10.1145/3449726.3463159"},{"abstract":[{"lang":"eng","text":"Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques."}],"publication":"IEEE Access","department":[{"_id":"78"}],"keyword":["Software Analysis","Abstract Interpretation","Custom Instruction","Hardware Verification"],"type":"journal_article","date_created":"2021-11-25T14:12:22Z","date_updated":"2023-01-18T08:34:50Z","publication_status":"published","author":[{"last_name":"Jakobs","first_name":"Marie-Christine","full_name":"Jakobs, Marie-Christine"},{"id":"22398","last_name":"Pauck","first_name":"Felix","full_name":"Pauck, Felix"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"full_name":"Wehrheim, Heike","last_name":"Wehrheim","first_name":"Heike","id":"573"},{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"}],"year":"2021","title":"Software/Hardware Co-Verification for Custom Instruction Set Processors","doi":"10.1109/ACCESS.2021.3131213","language":[{"iso":"eng"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901 - Subproject B4","_id":"12"}],"quality_controlled":"1","citation":{"short":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021).","chicago":"Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” <i>IEEE Access</i>, 2021. <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">https://doi.org/10.1109/ACCESS.2021.3131213</a>.","apa":"Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., &#38; Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. <i>IEEE Access</i>. <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">https://doi.org/10.1109/ACCESS.2021.3131213</a>","ieee":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” <i>IEEE Access</i>, 2021, doi: <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>.","ama":"Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. <i>IEEE Access</i>. Published online 2021. doi:<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>","bibtex":"@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware Co-Verification for Custom Instruction Set Processors}, DOI={<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>}, journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021} }","mla":"Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” <i>IEEE Access</i>, IEEE, 2021, doi:<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>."},"status":"public","user_id":"22398","_id":"27841","publisher":"IEEE","funded_apc":"1"},{"publication_status":"published","date_updated":"2023-04-19T15:03:45Z","title":"Hardware Trojans in Reconfigurable Computing","status":"public","year":"2021","author":[{"id":"72764","orcid":"0000-0002-1837-2254","last_name":"Ahmed","first_name":"Qazi Arbab","full_name":"Ahmed, Qazi Arbab"}],"user_id":"72764","doi":"10.1109/vlsi-soc53125.2021.9606974","language":[{"iso":"eng"}],"_id":"29138","project":[{"name":"SFB 901 - B: SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"},{"name":"SFB 901: SFB 901","_id":"1"}],"publication":"2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)","citation":{"short":"Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021.","chicago":"Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” In <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2021. <a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">https://doi.org/10.1109/vlsi-soc53125.2021.9606974</a>.","ieee":"Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: <a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>.","apa":"Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>. <a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">https://doi.org/10.1109/vlsi-soc53125.2021.9606974</a>","bibtex":"@inproceedings{Ahmed_2021, title={Hardware Trojans in Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>}, booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Ahmed, Qazi Arbab}, year={2021} }","ama":"Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>. ; 2021. doi:<a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>","mla":"Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” <i>2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2021, doi:<a href=\"https://doi.org/10.1109/vlsi-soc53125.2021.9606974\">10.1109/vlsi-soc53125.2021.9606974</a>."},"type":"conference","department":[{"_id":"78"}],"date_created":"2021-12-30T00:02:24Z"},{"department":[{"_id":"78"}],"type":"conference","date_created":"2020-12-07T14:03:00Z","file":[{"success":1,"content_type":"application/pdf","file_id":"44752","date_updated":"2023-05-11T09:16:15Z","relation":"main_file","access_level":"closed","file_size":394011,"file_name":"1812.pdf","date_created":"2023-05-11T09:16:15Z","creator":"qazi"}],"abstract":[{"text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques.","lang":"eng"}],"publication":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","doi":"10.23919/DATE51398.2021.9474026","language":[{"iso":"eng"}],"main_file_link":[{"open_access":"1"}],"date_updated":"2023-05-11T09:16:34Z","publication_status":"published","author":[{"id":"72764","full_name":"Ahmed, Qazi Arbab","last_name":"Ahmed","orcid":"0000-0002-1837-2254","first_name":"Qazi Arbab"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema","id":"3118"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"publication_identifier":{"eisbn":["978-3-9819263-5-4"]},"title":"Malicious Routing: Circumventing Bitstream-level Verification for FPGAs","year":"2021","oa":"1","place":"Alpexpo | Grenoble, France","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901","_id":"1"}],"citation":{"ama":"Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. 2021 Design, Automation and Test in Europe Conference (DATE); 2021. doi:<a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>","bibtex":"@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble, France}, title={Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}, DOI={<a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>}, booktitle={2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021} }","mla":"Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 2021 Design, Automation and Test in Europe Conference (DATE), 2021, doi:<a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>.","short":"Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.","chicago":"Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” In <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. Alpexpo | Grenoble, France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. <a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">https://doi.org/10.23919/DATE51398.2021.9474026</a>.","apa":"Ahmed, Q. A., Wiersema, T., &#38; Platzner, M. (2021). Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. <i>2021 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. <a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">https://doi.org/10.23919/DATE51398.2021.9474026</a>","ieee":"Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: <a href=\"https://doi.org/10.23919/DATE51398.2021.9474026\">10.23919/DATE51398.2021.9474026</a>."},"file_date_updated":"2023-05-11T09:16:15Z","ddc":["006"],"user_id":"72764","publisher":"2021 Design, Automation and Test in Europe Conference (DATE)","_id":"20681","has_accepted_license":"1","conference":{"location":"Alpexpo | Grenoble, France","start_date":"2021-02-01","name":"Design, Automation and Test in Europe Conference (DATE'21)","end_date":"2021-02-05"},"status":"public"},{"date_created":"2022-04-18T10:17:47Z","department":[{"_id":"78"}],"type":"conference","citation":{"mla":"Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip.” <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>, ACM, 2021, doi:<a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>.","bibtex":"@inproceedings{Clausing_2021, title={ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip}, DOI={<a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>}, booktitle={Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={ACM}, author={Clausing, Lennart}, year={2021} }","ama":"Clausing L. ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. In: <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. ACM; 2021. doi:<a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>","ieee":"L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,” 2021, doi: <a href=\"https://doi.org/10.1145/3468044.3468056\">10.1145/3468044.3468056</a>.","apa":"Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. <a href=\"https://doi.org/10.1145/3468044.3468056\">https://doi.org/10.1145/3468044.3468056</a>","short":"L. Clausing, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2021.","chicago":"Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip.” In <i>Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. ACM, 2021. <a href=\"https://doi.org/10.1145/3468044.3468056\">https://doi.org/10.1145/3468044.3468056</a>."},"publication":"Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"_id":"82","name":"SFB 901 - T: SFB 901 - Project Area T"},{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1","grant_number":"160364472"}],"language":[{"iso":"eng"}],"_id":"30909","publisher":"ACM","doi":"10.1145/3468044.3468056","user_id":"398","author":[{"full_name":"Clausing, Lennart","first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034","id":"74287"}],"status":"public","title":"ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip","year":"2021","date_updated":"2023-07-09T13:09:11Z","publication_status":"published"},{"publisher":"Springer","_id":"30908","language":[{"iso":"eng"}],"doi":"https://doi.org/10.1007/978-3-030-93736-2_27","user_id":"477","year":"2021","title":"FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics","status":"public","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","id":"61186"},{"orcid":"0000-0003-4987-5708","first_name":"Felix","last_name":"Jentzsch","full_name":"Jentzsch, Felix","id":"55631"},{"full_name":"Kuschel, Maurice","last_name":"Kuschel","first_name":"Maurice"},{"last_name":"Arshad","first_name":"Rahil ","full_name":"Arshad, Rahil "},{"first_name":"Sneha","last_name":"Rautmare","full_name":"Rautmare, Sneha"},{"full_name":"Manjunatha, Suraj","first_name":"Suraj","last_name":"Manjunatha"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"},{"first_name":"Dirk ","last_name":"Schollbach","full_name":"Schollbach, Dirk "}],"date_updated":"2023-09-15T15:09:07Z","date_created":"2022-04-18T10:16:55Z","type":"conference","department":[{"_id":"78"}],"publication":" Machine Learning and Principles and Practice of Knowledge Discovery in Databases","citation":{"chicago":"Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil  Arshad, Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk  Schollbach. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” In <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. Springer, 2021. <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>.","short":"H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare, S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in:  Machine Learning and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.","apa":"Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare, S., Manjunatha, S., Platzner, M., Boschmann, A., &#38; Schollbach, D. (2021). FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>","ieee":"H. Ghasemzadeh Mohammadi <i>et al.</i>, “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,” 2021, doi: <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>.","ama":"Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. In: <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. Springer; 2021. doi:<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021, title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics}, DOI={<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>}, booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil  and Rautmare, Sneha and Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk }, year={2021} }","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>, Springer, 2021, doi:<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>."},"project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"}]},{"department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"type":"conference","date_created":"2018-07-20T14:07:15Z","citation":{"ieee":"Z.  Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2020.","mla":"Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2020.","apa":"Guetttatfi, Z., Kaufmann, P., &#38; Platzner, M. (2020). Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>.","bibtex":"@inproceedings{ Guetttatfi_Kaufmann_Platzner_2020, title={Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices}, booktitle={Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}, author={ Guetttatfi, Zakarya and Kaufmann, Paul and Platzner, Marco}, year={2020} }","ama":"Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In: <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. ; 2020.","short":"Z.  Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.","chicago":"Guetttatfi, Zakarya, Paul Kaufmann, and Marco Platzner. “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2020."},"publication":"Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)","user_id":"398","_id":"3583","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:59:25Z","author":[{"full_name":" Guetttatfi, Zakarya","last_name":" Guetttatfi","first_name":"Zakarya"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"status":"public","title":"Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices","year":"2020"},{"user_id":"49051","_id":"21324","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:54:54Z","title":"Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis","status":"public","year":"2020","author":[{"full_name":"Chandrakar, Khushboo","last_name":"Chandrakar","first_name":"Khushboo"}],"type":"mastersthesis","department":[{"_id":"78"},{"_id":"7"}],"date_created":"2021-03-01T09:19:29Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"citation":{"chicago":"Chandrakar, Khushboo. <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>, 2020.","short":"K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis, 2020.","ieee":"K. Chandrakar, <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>. 2020.","apa":"Chandrakar, K. (2020). <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>.","bibtex":"@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020} }","ama":"Chandrakar K. <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>.; 2020.","mla":"Chandrakar, Khushboo. <i>Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis</i>. 2020."},"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"id":"49051","last_name":"Witschen","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias"}]},{"abstract":[{"text":"Robots are becoming increasingly autonomous and more capable. Because of a limited portable energy budget by e.g. batteries, and more demanding algorithms, an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs) for example can provide fast and efficient processing and the Robot Operating System (ROS) is a popular\r\nmiddleware used for robotic applications. The novel ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework for integrating reconfigurable hardware. It provides a unified interface between software and hardware. ReconROS is evaluated in this thesis by implementing a Sobel filter as the video processing application, running on a Zynq-7000 series System on Chip. Timing measurements were taken of execution and transfer times and were compared to theoretical values. Designing the hardware implementation is done by C code using High Level Synthesis and with the interface and functionality provided by ReconROS. An important aspect is the publish/subscribe mechanism of ROS. The Operating System interface functions for publishing and subscribing are reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces consistency to the execution times and performs twice as fast as the software implementation.","lang":"eng"}],"citation":{"ama":"Henke L-S. <i>Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application</i>.; 2020.","bibtex":"@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020} }","mla":"Henke, Luca-Sebastian. <i>Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application</i>. 2020.","chicago":"Henke, Luca-Sebastian. <i>Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application</i>, 2020.","short":"L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application, 2020.","apa":"Henke, L.-S. (2020). <i>Evaluation of a ReconOS-ROS Combination based on a Video Processing Application</i>.","ieee":"L.-S. Henke, <i>Evaluation of a ReconOS-ROS Combination based on a Video Processing Application</i>. 2020."},"supervisor":[{"full_name":"Lienen, Christian","first_name":"Christian","last_name":"Lienen","id":"60323"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"type":"bachelorsthesis","date_created":"2021-03-10T07:07:01Z","date_updated":"2022-01-06T06:54:59Z","author":[{"full_name":"Henke, Luca-Sebastian","last_name":"Henke","first_name":"Luca-Sebastian"}],"title":"Evaluation of a ReconOS-ROS Combination based on a Video Processing Application","year":"2020","status":"public","user_id":"60323","language":[{"iso":"eng"}],"_id":"21432"},{"publication":"Machine Learning for Cyber Physical Systems (ML4CPS 2017)","citation":{"ama":"Gatica CP, Platzner M. Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures. In: <i>Machine Learning for Cyber Physical Systems (ML4CPS 2017)</i>. Berlin, Heidelberg; 2020. doi:<a href=\"https://doi.org/10.1007/978-3-662-59084-3_9\">10.1007/978-3-662-59084-3_9</a>","bibtex":"@inproceedings{Gatica_Platzner_2020, place={Berlin, Heidelberg}, title={Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures}, DOI={<a href=\"https://doi.org/10.1007/978-3-662-59084-3_9\">10.1007/978-3-662-59084-3_9</a>}, booktitle={Machine Learning for Cyber Physical Systems (ML4CPS 2017)}, author={Gatica, Carlos Paiz and Platzner, Marco}, year={2020} }","mla":"Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” <i>Machine Learning for Cyber Physical Systems (ML4CPS 2017)</i>, 2020, doi:<a href=\"https://doi.org/10.1007/978-3-662-59084-3_9\">10.1007/978-3-662-59084-3_9</a>.","chicago":"Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” In <i>Machine Learning for Cyber Physical Systems (ML4CPS 2017)</i>. Berlin, Heidelberg, 2020. <a href=\"https://doi.org/10.1007/978-3-662-59084-3_9\">https://doi.org/10.1007/978-3-662-59084-3_9</a>.","short":"C.P. Gatica, M. Platzner, in: Machine Learning for Cyber Physical Systems (ML4CPS 2017), Berlin, Heidelberg, 2020.","apa":"Gatica, C. P., &#38; Platzner, M. (2020). Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures. In <i>Machine Learning for Cyber Physical Systems (ML4CPS 2017)</i>. Berlin, Heidelberg. <a href=\"https://doi.org/10.1007/978-3-662-59084-3_9\">https://doi.org/10.1007/978-3-662-59084-3_9</a>","ieee":"C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures,” in <i>Machine Learning for Cyber Physical Systems (ML4CPS 2017)</i>, 2020."},"type":"conference","department":[{"_id":"78"}],"date_created":"2021-03-31T08:58:59Z","place":"Berlin, Heidelberg","publication_status":"published","date_updated":"2022-01-06T06:55:06Z","year":"2020","title":"Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures","status":"public","author":[{"full_name":"Gatica, Carlos Paiz","last_name":"Gatica","first_name":"Carlos Paiz"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"publication_identifier":{"isbn":["9783662590836","9783662590843"],"issn":["2522-8579","2522-8587"]},"user_id":"398","doi":"10.1007/978-3-662-59084-3_9","_id":"21584","language":[{"iso":"eng"}]},{"citation":{"apa":"Witschen, L. M., Wiersema, T., &#38; Platzner, M. (2020). Proof-carrying Approximate Circuits. <i>IEEE Transactions On Very Large Scale Integration Systems</i>, <i>28</i>(9), 2084–2088. <a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">https://doi.org/10.1109/TVLSI.2020.3008061</a>","mla":"Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” <i>IEEE Transactions On Very Large Scale Integration Systems</i>, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>.","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” <i>IEEE Transactions On Very Large Scale Integration Systems</i>, vol. 28, no. 9, pp. 2084–2088, 2020.","ama":"Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. <i>IEEE Transactions On Very Large Scale Integration Systems</i>. 2020;28(9):2084-2088. doi:<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>","short":"L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” <i>IEEE Transactions On Very Large Scale Integration Systems</i> 28, no. 9 (2020): 2084–88. <a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">https://doi.org/10.1109/TVLSI.2020.3008061</a>.","bibtex":"@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }"},"quality_controlled":"1","project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901","_id":"1"}],"page":"2084 - 2088","publisher":"IEEE","_id":"17358","funded_apc":"1","user_id":"49051","volume":28,"status":"public","date_created":"2020-07-06T11:21:30Z","type":"journal_article","keyword":["Approximate circuit synthesis","approximate computing","error metrics","formal verification","proof-carrying hardware"],"department":[{"_id":"78"}],"issue":"9","publication":"IEEE Transactions On Very Large Scale Integration Systems","abstract":[{"text":"Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/TVLSI.2020.3008061","year":"2020","title":"Proof-carrying Approximate Circuits","author":[{"full_name":"Witschen, Linus Matthias","last_name":"Witschen","first_name":"Linus Matthias","id":"49051"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema","id":"3118"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"publication_identifier":{"issn":["1063-8210"],"eissn":["1557-9999"]},"date_updated":"2022-01-06T06:53:09Z","publication_status":"published","intvolume":"        28","article_type":"original"},{"user_id":"398","_id":"17369","publisher":"IOS Press","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:53:09Z","year":"2020","title":"Evolution of Application-Specific Cache Mappings","status":"public","author":[{"full_name":"Ho, Nam","last_name":"Ho","first_name":"Nam"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"type":"journal_article","department":[{"_id":"78"}],"date_created":"2020-07-10T18:55:30Z","publication":"International Journal of Hybrid intelligent Systems","citation":{"bibtex":"@article{Ho_Kaufmann_Platzner_2020, title={Evolution of Application-Specific Cache Mappings}, journal={International Journal of Hybrid intelligent Systems}, publisher={IOS Press}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2020} }","ama":"Ho N, Kaufmann P, Platzner M. Evolution of Application-Specific Cache Mappings. <i>International Journal of Hybrid intelligent Systems</i>. 2020.","mla":"Ho, Nam, et al. “Evolution of Application-Specific Cache Mappings.” <i>International Journal of Hybrid Intelligent Systems</i>, IOS Press, 2020.","short":"N. Ho, P. Kaufmann, M. Platzner, International Journal of Hybrid Intelligent Systems (2020).","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolution of Application-Specific Cache Mappings.” <i>International Journal of Hybrid Intelligent Systems</i>, 2020.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” <i>International Journal of Hybrid intelligent Systems</i>, 2020.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2020). Evolution of Application-Specific Cache Mappings. <i>International Journal of Hybrid Intelligent Systems</i>."}},{"user_id":"3118","ddc":["000"],"_id":"20748","page":"2","has_accepted_license":"1","status":"public","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901","_id":"1"}],"citation":{"mla":"Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.” <i>Fifth Workshop on Approximate Computing (AxC 2020)</i>.","bibtex":"@article{Witschen_Wiersema_Platzner, title={Search Space Characterization for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }","ama":"Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC Synthesis. <i>Fifth Workshop on Approximate Computing (AxC 2020)</i>.","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” <i>Fifth Workshop on Approximate Computing (AxC 2020)</i>. .","apa":"Witschen, L. M., Wiersema, T., &#38; Platzner, M. (n.d.). Search Space Characterization for AxC Synthesis. <i>Fifth Workshop on Approximate Computing (AxC 2020)</i>.","short":"L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing (AxC 2020) (n.d.).","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search Space Characterization for AxC Synthesis.” <i>Fifth Workshop on Approximate Computing (AxC 2020)</i>, n.d."},"file_date_updated":"2020-12-15T15:11:06Z","language":[{"iso":"eng"}],"publication_status":"accepted","date_updated":"2022-01-06T06:54:35Z","author":[{"first_name":"Linus Matthias","last_name":"Witschen","full_name":"Witschen, Linus Matthias","id":"49051"},{"id":"3118","last_name":"Wiersema","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"title":"Search Space Characterization for AxC Synthesis","year":"2020","department":[{"_id":"78"}],"type":"preprint","date_created":"2020-12-15T15:13:49Z","file":[{"creator":"witschen","date_created":"2020-12-15T15:11:06Z","date_updated":"2020-12-15T15:11:06Z","relation":"main_file","access_level":"closed","file_size":250870,"file_name":"witschen20_axc.pdf","content_type":"application/pdf","success":1,"file_id":"20749"}],"abstract":[{"lang":"eng","text":"On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies.\r\nIn the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. \r\nIn this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification.\r\nIn our experimental results, we present the runtimes of our approach."}],"publication":"Fifth Workshop on Approximate Computing (AxC 2020)"},{"citation":{"ieee":"C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for ROS2 Applications,” in <i>Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)</i>, 2020.","apa":"Lienen, C., Platzner, M., &#38; Rinner, B. (2020). ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In <i>Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)</i>.","chicago":"Lienen, Christian, Marco Platzner, and Bernhard Rinner. “ReconROS: Flexible Hardware Acceleration for ROS2 Applications.” In <i>Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)</i>, 2020.","short":"C. Lienen, M. Platzner, B. Rinner, in: Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.","mla":"Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for ROS2 Applications.” <i>Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)</i>, 2020.","bibtex":"@inproceedings{Lienen_Platzner_Rinner_2020, title={ReconROS: Flexible Hardware Acceleration for ROS2 Applications}, booktitle={Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)}, author={Lienen, Christian and Platzner, Marco and Rinner, Bernhard}, year={2020} }","ama":"Lienen C, Platzner M, Rinner B. ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In: <i>Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)</i>. ; 2020."},"publication":"Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)","department":[{"_id":"78"}],"type":"conference","date_created":"2020-12-16T05:20:01Z","date_updated":"2022-01-06T06:54:35Z","conference":{"end_date":"2020-12-11","start_date":"2020-12-09","name":"International Conference on Field Programmable Technology (ICFPT)"},"author":[{"id":"60323","first_name":"Christian","last_name":"Lienen","full_name":"Lienen, Christian"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Rinner, Bernhard","last_name":"Rinner","first_name":"Bernhard"}],"title":"ReconROS: Flexible Hardware Acceleration for ROS2 Applications","status":"public","year":"2020","user_id":"398","_id":"20750","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:54:40Z","author":[{"full_name":"Thiele, Simon","last_name":"Thiele","first_name":"Simon"}],"title":"Implementing Machine Learning Functions as PYNQ FPGA Overlays","year":"2020","status":"public","user_id":"74287","language":[{"iso":"eng"}],"_id":"20820","project":[{"name":"SFB 901","_id":"1"},{"_id":"82","name":"SFB 901 - Project Area T"},{"name":"SFB 901 -Subproject T1","_id":"83"}],"supervisor":[{"id":"74287","full_name":"Clausing, Lennart","first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"}],"citation":{"short":"S. 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