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Hardware Trojans in Reconfigurable Computing. Paderborn University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.","bibtex":"@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable Computing}, DOI={10.17619/UNIPB/1-1271}, publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab}, year={2022} }","chicago":"Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.","ama":"Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University, Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271","apa":"Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271","ieee":"Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn University, Paderborn, Germany, 2022.","short":"Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University, Paderborn, Germany, Paderborn, 2022."},"abstract":[{"lang":"eng","text":"Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden."},{"text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable systems, the defenders perspective which corresponds to the bitstream-level Trojan detection technique, and the attackers perspective which corresponds to a novel FPGA Trojan attack. From the defender's perspective, we introduce a first-ever successful pre-configuration countermeasure against the ``Malicious LUT''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers perspective, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by bitstream-level verification techniques.","lang":"eng"}],"user_id":"477","ddc":["004"],"keyword":["FPGA Security","Hardware Trojans","Bitstream-level Trojans","Bitstream Verification"],"publisher":" Paderborn University, Paderborn, Germany","author":[{"orcid":"0000-0002-1837-2254","full_name":"Ahmed, Qazi Arbab","first_name":"Qazi Arbab","id":"72764","last_name":"Ahmed"}],"date_created":"2022-02-07T14:02:36Z","has_accepted_license":"1","status":"public","date_updated":"2022-11-30T13:39:01Z","oa":"1","doi":"10.17619/UNIPB/1-1271","language":[{"iso":"eng"}],"place":"Paderborn","title":"Hardware Trojans in Reconfigurable Computing","department":[{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"name":"SFB 901 - C2: SFB 901 - Subproject C2","_id":"14"}],"publication_status":"published"},{"citation":{"ieee":"C. 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Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy."}},{"doi":"10.1109/DSD57027.2022.00088","conference":{"location":"Maspalomas, Gran Canaria, Spain","name":"25th Euromicro Conference on Digital System Design (DSD)"},"date_updated":"2023-01-06T06:38:27Z","_id":"34005","type":"conference","year":"2022","citation":{"short":"C. Lienen, M. Platzner, in: 2022 25th Euromicro Conference on Digital System Design (DSD), n.d.","ieee":"C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,” presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi: 10.1109/DSD57027.2022.00088.","apa":"Lienen, C., & Platzner, M. (n.d.). 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