TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - JOUR AU - Thielemans, Kris AU - Tsoumpas, Charalampos AU - Mustafovic, Sanida AU - Beisel, Tobias AU - Aguiar, Pablo AU - Dikaios, Nikolaos AU - W Jacobson, Matthew ID - 2172 IS - 4 JF - Physics in Medicine and Biology TI - STIR: Software for Tomographic Image Reconstruction Release 2 VL - 57 ER - TY - JOUR AU - Redif, Soydan AU - Kasap, Server ID - 2173 IS - 12 JF - Int. Journal of Electronics TI - Parallel algorithm for computation of second-order sequential best rotations VL - 100 ER - TY - JOUR AU - Kasap, Server AU - Benkrid, Khaled ID - 2174 IS - 6 JF - Journal of Computers TI - Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer VL - 7 ER - TY - THES AB - FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety. AU - Drzevitzky, Stephanie ID - 586 TI - Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security ER - TY - GEN AU - Plessl, Christian AU - Platzner, Marco AU - Agne, Andreas AU - Happe, Markus AU - Lübbers, Enno ID - 587 TI - Programming models for reconfigurable heterogeneous multi-cores ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10636 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array ER -