TY - CHAP AU - Walker, James Alfred AU - Miller, Julian F. AU - Kaufmann, Paul AU - Platzner, Marco ID - 10748 T2 - Cartesian Genetic Programming TI - Problem Decomposition in Cartesian Genetic Programming ER - TY - GEN AU - Welp, Daniel ID - 10750 TI - User Space Scheduling for Heterogeneous Systems ER - TY - CONF AU - Agne, Andreas AU - Platzner, Marco AU - Lübbers, Enno ID - 13643 SN - 9781457714849 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Memory Virtualization for Multithreaded Reconfigurable Hardware ER - TY - CONF AU - Henkel, Jörg AU - Hedrich, Lars AU - Herkersdorf, Andreas AU - Kapitza, Rüdiger AU - Lohmann, Daniel AU - Marwedel, Peter AU - Platzner, Marco AU - Rosenstiel, Wolfgang AU - Schlichtmann, Ulf AU - Spinczyk, Olaf AU - Tahoori, Mehdi AU - Bauer, Lars AU - Teich, Jürgen AU - Wehn, Norbert AU - Wunderlich, Hans-Joachim AU - Becker, Joachim AU - Bringmann, Oliver AU - Brinkschulte, Uwe AU - Chakraborty, Samarjit AU - Engel, Michael AU - Ernst, Rolf AU - Härtig, Hermann ID - 13644 SN - 9781450307154 T2 - Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11 TI - Design and architectures for dependable embedded systems ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - JOUR AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2201 JF - Int. Journal of Recon- figurable Computing (IJRC) KW - funding-altera TI - FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER -