TY - JOUR AB - Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2412 IS - 2-3 JF - Microprocessors and Microsystems KW - FPGA KW - reconfigurable computing KW - co-simulation KW - Zippy TI - System-level performance evaluation of reconfigurable processors VL - 29 ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13621 SN - 3902463031 T2 - Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES) TI - Periodic real-time scheduling for FPGA computers ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13622 T2 - Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS) TI - Memory-demanding Periodic Real-time Applications on FPGA Computers ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13623 SN - 0780393627 T2 - Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL) TI - A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware ER - TY - CONF AB - In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. AU - Plessl, Christian AU - Platzner, Marco ID - 2415 KW - hardware virtualization T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Virtualization of Hardware – Introduction and Survey ER - TY - JOUR AU - Steiger, Christoph AU - Walder, Herbert AU - Platzner, Marco ID - 10742 IS - 11 JF - {IEEE} Transactions on Computers TI - Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks VL - 53 ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13618 SN - 0302-9743 T2 - Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) TI - A Runtime Environment for Reconfigurable Hardware Operating Systems ER - TY - CONF AU - Walder, Hebert AU - Nobs, Samuel AU - Platzner, Marco ID - 13619 T2 - Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems ER - TY - CONF AU - Dyer, Matthias AU - Platzner, Marco AU - Thiele, Lothar ID - 13620 SN - 0769522300 T2 - Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) TI - Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine ER - TY - CONF AB - This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. AU - Plessl, Christian AU - Platzner, Marco ID - 2418 KW - coprocessor KW - DIMM KW - memory bus KW - FPGA KW - high performance computing T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - TKDM – A Reconfigurable Co-processor in a PC's Memory Slot ER -