TY - CONF AB - Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. AU - Dyer, Matthias AU - Plessl, Christian AU - Platzner, Marco ID - 2424 KW - partial reconfiguration T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Partially Reconfigurable Cores for Xilinx Virtex VL - 2438 ER - TY - CONF AB - We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. AU - Plessl, Christian AU - Platzner, Marco ID - 2425 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - Custom Computing Machines for the Set Covering Problem ER - TY - JOUR AU - Eisenring, Michael AU - Platzner, Marco ID - 10651 IS - 2 JF - The Journal of Supercomputing TI - A Framework for Run-time Reconfigurable Systems VL - 21 ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13611 T2 - Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform ER - TY - CONF AB - In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. AU - Plessl, Christian AU - Platzner, Marco ID - 2428 KW - minimum covering KW - accelerator KW - funding-sundance T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Instance-Specific Accelerators for Minimum Covering ER - TY - CONF AB - In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core. AU - Enzler, Rolf AU - Platzner, Marco AU - Plessl, Christian AU - Thiele, Lothar AU - Tröster, Gerhard ID - 2432 KW - benchmark T2 - Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III TI - Reconfigurable Processors for Handhelds and Wearables: Application Analysis VL - 4525 ER - TY - JOUR AU - Mencer, Oskar AU - Platzner, Marco AU - Morf, Martin AU - J. Flynn, Michael ID - 10713 IS - 1 JF - {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems TI - Object-oriented domain specific compilers for programming FPGAs VL - 9 ER - TY - GEN AU - Enzler, Rolf AU - Platzner, Marco ID - 13463 TI - Dynamically Reconfigurable Processors ER - TY - JOUR AU - Platzner, Marco ID - 6507 IS - 4 JF - Computer SN - 0018-9162 TI - Reconfigurable accelerators for combinatorial problems VL - 33 ER - TY - JOUR AU - Eisenring, Michael AU - Platzner, Marco ID - 10606 JF - IEE Proceedings -- Computers & Digital Techniques TI - Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems VL - 147 ER -