TY - GEN AB - Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis. AU - Keerthipati, Monica ID - 15920 TI - A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking ER - TY - GEN AU - Sabu, Nithin S. ID - 14831 TI - FPGA Acceleration of String Search Techniques in Huge Data Sets ER - TY - GEN AU - Mehta, Jinay ID - 15946 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip ER - TY - GEN AU - Hansmeier, Tim ID - 14546 TI - Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers ER - TY - CONF AU - Guettatfi, Zakarya AU - Platzner, Marco AU - Kermia, Omar AU - Khouas, Abdelhakim ID - 31067 T2 - 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) TI - An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware ER - TY - CONF AB - Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers. AU - Ahmed, Qazi Arbab AU - Wiersema, Tobias AU - Platzner, Marco ED - Hochberger, Christian ED - Nelson, Brent ED - Koch, Andreas ED - Woods, Roger ED - Diniz, Pedro ID - 9913 SN - 978-3-030-17227-5 T2 - Applied Reconfigurable Computing TI - Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan VL - 11444 ER - TY - GEN AU - Lienen, Christian ID - 15874 TI - Implementing a Real-time System on a Platform FPGA operated with ReconOS ER - TY - JOUR AU - Platzner, Marco AU - Plessl, Christian ID - 12871 JF - Informatik Spektrum SN - 0170-6012 TI - FPGAs im Rechenzentrum ER - TY - GEN AU - Mehta, Jinay D ID - 52478 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip ER - TY - CONF AB - Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node. AU - Lösch, Achim AU - Wiens, Alex AU - Platzner, Marco ID - 3362 SN - 0302-9743 T2 - Proceedings of the International Conference on Architecture of Computing Systems (ARCS) TI - Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes VL - 10793 ER -