TY - CONF AU - Kaufmann, Paul AU - Ho, Nam AU - Platzner, Marco ID - 10761 T2 - Adaptive Hardware and Systems (AHS) TI - Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10762 T2 - Genetic and Evolutionary Computation (GECCO), Compendium TI - An Empirical Study on the Parametrization of Cartesian Genetic Programming ER - TY - CONF AU - Guettatfi, Zakarya AU - Hübner, Philipp AU - Platzner, Marco AU - Rinner, Bernhard ID - 10780 KW - embedded systems KW - image sensors KW - power aware computing KW - wireless sensor networks KW - Zynq-based VSN node prototype KW - computational self-awareness KW - design approach KW - platform levels KW - power consumption KW - visual sensor networks KW - visual sensor nodes KW - Cameras KW - Hardware KW - Middleware KW - Multicore processing KW - Operating systems KW - Runtime KW - Reconfigurable platforms KW - distributed embedded systems KW - performance-resource trade-off KW - self-awareness KW - visual sensor nodes T2 - 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Computational self-awareness as design approach for visual sensor nodes ER - TY - CONF AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Platzner, Marco ID - 14893 SN - 1865-0929 T2 - Communications in Computer and Information Science TI - I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems ER - TY - JOUR AB - Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved. AU - Wiersema, Tobias AU - Bockhorn, Arne AU - Platzner, Marco ID - 222 JF - Computers & Electrical Engineering TI - An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 5812 SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - GEN AU - Cedric Mertens, Jan ID - 10612 TI - Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion ER - TY - GEN AU - Nassery, Abdul Sami ID - 10616 TI - Implementation of Bilinear Pairings on Reconfigurable Hardware ER - TY - GEN AU - Amin, Omair ID - 10617 TI - Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10622 T2 - Euromicro Conference on Digital System Design (DSD) TI - Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs ER - TY - CONF AU - Boschmann, Alexander AU - Dosen, Strahinja AU - Werner, Andreas AU - Raies, Ali AU - Farina, Dario ID - 10631 T2 - Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI) TI - A novel immersive augmented reality system for prosthesis training and assessment ER - TY - JOUR AU - Graf, Tobias AU - Platzner, Marco ID - 10661 JF - Journal Theoretical Computer Science TI - Adaptive playouts for online learning of policies during Monte Carlo Tree Search VL - 644 ER - TY - GEN AU - Horstmann, Jens ID - 10695 TI - Beschleunigte Simulation elektrischer Stromnetze mit GPUs ER - TY - JOUR AU - Ma, Chenjie AU - Kaufmann, Paul AU - Töbermann, J.-Christian AU - Braun, Martin ID - 10705 IS - (part 2) JF - Renewable Energy TI - Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control VL - 87 ER - TY - GEN AU - Makeswaran, Vignesh ID - 10706 TI - Operating System Support for Reconfigurable Cache ER - TY - GEN AU - Ibne Ashraf, Ishraq ID - 10707 TI - Private/Shared Data Classification and Implementation for a Multi-Softcore Platform ER - TY - CONF AU - Meisner, Sebastian AU - Platzner, Marco ID - 10712 T2 - Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on TI - Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level ER - TY - GEN AU - Schmidt, Marco ID - 10755 TI - Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10758 TI - Applications of Evolutionary Computation - 19th European Conference, EvoApplications VL - 9597 ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10766 T2 - Proceedings of the 30th European Simulation and Modelling Conference (ESM) TI - RCo-Design: New Visual Environment for Reconfigurable Embedded Systems ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10768 T2 - Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) TI - New Co-design Methodology for Real-time Embedded Systems ER - TY - JOUR AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10769 IS - 99 JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems TI - Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation VL - PP ER - TY - GEN AU - Hermansen, Sven ID - 10781 TI - Custom Memory Controller for ReconOS ER - TY - BOOK AB - Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering. ED - Lewis, Peter R. ED - Platzner, Marco ED - Rinner, Bernhard ED - Tørresen, Jim ED - Yao, Xin ID - 12972 SN - 1619-7127 TI - Self-aware Computing Systems: An Engineering Approach ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus Matthias AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 15873 KW - Electromyography KW - Feature extraction KW - Delays KW - Hardware Pattern recognition KW - Prosthetics KW - High definition video SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13151 T2 - Computer and Games TI - Using Deep Convolutional Neural Networks in Monte Carlo Tree Search ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13152 T2 - IEEE Computational Intelligence and Games TI - Monte-Carlo Simulation Balancing Revisited ER - TY - CONF AB - Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module. AU - Wiersema, Tobias AU - Platzner, Marco ID - 132 T2 - Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) TI - Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware ER - TY - CHAP AB - In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. AU - Agne, Andreas AU - Platzner, Marco AU - Plessl, Christian AU - Happe, Markus AU - Lübbers, Enno ED - Koch, Dirk ED - Hannig, Frank ED - Ziener, Daniel ID - 29 SN - 978-3-319-26406-6 T2 - FPGAs for Software Programmers TI - ReconOS ER - TY - CHAP AB - Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 156 T2 - Self-aware Computing Systems TI - Self-aware Compute Nodes ER - TY - CONF AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. AU - Lösch, Achim AU - Beisel, Tobias AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 168 T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center ER - TY - CONF AB - Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level. AU - Wiersema, Tobias AU - Wu, Sen AU - Platzner, Marco ID - 269 T2 - Proceedings of the International Symposium in Reconfigurable Computing (ARC) TI - On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach ER - TY - GEN AU - Knorr, Christoph ID - 3364 TI - Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten ER - TY - JOUR AU - Torresen, Jim AU - Plessl, Christian AU - Yao, Xin ID - 1772 IS - 7 JF - IEEE Computer KW - self-awareness KW - self-expression TI - Self-Aware and Self-Expressive Systems – Guest Editor's Introduction VL - 48 ER - TY - GEN AU - Ahmed, Abdullah Fathi ID - 10615 TI - Self-Optimizing Organic Cache ER - TY - THES AB - The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies. AU - Beisel, Tobias ID - 10624 SN - 978-3-8325-4155-2 TI - Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing ER - TY - GEN AU - Hangmann, Hendrik ID - 10668 TI - Evolution of Heat Flow Prediction Models for FPGA Devices ER - TY - GEN AU - Haupt, Christian ID - 10671 TI - Computer Vision basierte Klassifikation von HD EMG Signalen ER - TY - CONF AU - Ho, Nam AU - Ahmed, Abdullah Fathi AU - Kaufmann, Paul AU - Platzner, Marco ID - 10673 KW - cache storage KW - field programmable gate arrays KW - multiprocessing systems KW - parallel architectures KW - reconfigurable architectures KW - FPGA KW - dynamic reconfiguration KW - evolvable cache mapping KW - many-core architecture KW - memory-to-cache address mapping function KW - microarchitectural optimization KW - multicore architecture KW - nature-inspired optimization KW - parallelization degrees KW - processor KW - reconfigurable cache mapping KW - reconfigurable computing KW - Field programmable gate arrays KW - Software KW - Tuning T2 - Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) TI - Microarchitectural optimization by means of reconfigurable and evolvable cache mappings ER - TY - CONF AU - Kaufmann, Paul AU - Shen, Cong ID - 10693 T2 - Genetic and Evolutionary Computation (GECCO) TI - Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing ER - TY - CONF AU - Meisner, Sebastian AU - Platzner, Marco ID - 10711 T2 - Field Programmable Technology (FPT), 2015 International Conference on TI - Comparison of thread signatures for error detection in hybrid multi-cores ER - TY - GEN AU - Meißner, Roland ID - 10714 TI - Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs ER - TY - GEN AU - Posewsky, Thorbjörn ID - 10726 TI - Acceleration of Artificial Neural Networks on a Zynq Platform ER - TY - BOOK AU - M. Mora, Antonio AU - Squillero, Giovanni AU - Agapitos, Alexandros AU - Burelli, Paolo AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10757 TI - Applications of Evolutionary Computation - 18th European Conference, EvoApplications VL - 9028 ER - TY - CONF AU - H.W. Leong, Philip AU - Amano, Hideharu AU - Anderson, Jason AU - Bertels, Koen AU - M.P. Cardoso, Jo\~ao AU - Diessel, Oliver AU - Gogniat, Guy AU - Hutton, Mike AU - Lee, JunKyu AU - Luk, Wayne AU - Lysaght, Patrick AU - Platzner, Marco AU - K. Prasanna, Viktor AU - Rissa, Tero AU - Silvano, Cristina AU - So, Hayden AU - Wang, Yu ID - 10765 T2 - Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) TI - Significant papers from the first 25 years of the FPL conference ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10767 T2 - Proceedings of the 29th European Simulation and Modelling Conference (ESM) TI - New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software ER - TY - JOUR AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10770 IS - 6 JF - IEEE Transactions on Nanotechnology TI - From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires VL - 14 ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Zhang, Jian AU - De Micheli, Giovanni AU - Sanchez, Eduardo AU - Reorda, Matteo Sonza ID - 10771 T2 - 2015 IEEE Computer Society Annual Symposium on VLSI TI - On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10772 T2 - Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition TI - Fault modeling in controllable polarity silicon nanowire circuits ER - TY - CONF AU - Guettatfi, Zakarya AU - Kermia, Omar AU - Khouas, Abdelhakim ID - 10779 KW - embedded systems KW - field programmable gate arrays KW - operating systems (computers) KW - scheduling KW - μC/OS-II KW - FPGAs KW - OS foundation KW - SafeRTOS KW - Xenomai KW - chip utilization ration KW - complex time constraints KW - embedded systems KW - hard real-time hardware task allocation KW - hard real-time hardware task scheduling KW - hardware-software real-time operating systems KW - partially reconfigurable field-programmable gate arrays KW - resource constraints KW - safety-critical RTOS KW - Field programmable gate arrays KW - Hardware KW - Job shop scheduling KW - Real-time systems KW - Shape KW - Software SN - 1946-147X T2 - 25th International Conference on Field Programmable Logic and Applications (FPL) TI - Over effective hard real-time hardware tasks scheduling and allocation ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13153 T2 - Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers TI - Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning ER - TY - JOUR AB - FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 296 JF - International Journal of Reconfigurable Computing (IJRC) TI - Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study VL - 2015 ER - TY - CONF AB - This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. AU - Damschen, Marvin AU - Plessl, Christian ID - 303 T2 - Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) TI - Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores ER - TY - CONF AU - Schumacher, Jörn AU - T. Anderson, J. AU - Borga, A. AU - Boterenbrood, H. AU - Chen, H. AU - Chen, K. AU - Drake, G. AU - Francis, D. AU - Gorini, B. AU - Lanni, F. AU - Lehmann-Miotto, Giovanna AU - Levinson, L. AU - Narevicius, J. AU - Plessl, Christian AU - Roich, A. AU - Ryu, S. AU - P. Schreuder, F. AU - Vandelli, Wainer AU - Vermeulen, J. AU - Zhang, J. ID - 1773 T2 - Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) TI - Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm ER - TY - JOUR AU - Plessl, Christian AU - Platzner, Marco AU - Schreier, Peter J. ID - 1768 IS - 5 JF - Informatik Spektrum KW - approximate computing KW - survey TI - Aktuelles Schlagwort: Approximate Computing ER - TY - CONF AB - In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. AU - Damschen, Marvin AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 238 T2 - Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) TI - Transparent offloading of computational hotspots from binary code to Xeon Phi ER - TY - CONF AB - Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead. AU - Meisner, Sebastian AU - Platzner, Marco ED - Goehringer, Diana ED - Santambrogio, MarcoDomenico ED - Cardoso, JoãoM.P. ED - Bertels, Koen ID - 347 T2 - Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC) TI - Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection ER - TY - CONF AU - Graf, Tobias AU - Schaefers, Lars AU - Platzner, Marco ID - 1782 IS - 8427 T2 - Proc. Conf. on Computers and Games (CG) TI - On Semeai Detection in Monte-Carlo Go ER - TY - CONF AB - Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric. AU - Wiersema, Tobias AU - Drzevitzky, Stephanie AU - Platzner, Marco ID - 399 T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring ER - TY - CONF AB - Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques. AU - Jakobs, Marie-Christine AU - Platzner, Marco AU - Wiersema, Tobias AU - Wehrheim, Heike ED - Albert, Elvira ED - Sekerinski, Emil ID - 408 T2 - Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) TI - Integrating Software and Hardware Verification ER - TY - CONF AB - Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA. AU - Wiersema, Tobias AU - Bockhorn, Arne AU - Platzner, Marco ID - 433 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA ER - TY - JOUR AU - Schaefers, Lars AU - Platzner, Marco ID - 10602 IS - 3 JF - IEEE Transactions on Computational Intelligence and AI in Games TI - A Novel Technique and its Application to Computer Go VL - 6 ER - TY - JOUR AU - Giefers, Heiner AU - Platzner, Marco ID - 10603 IS - 12 JF - IEEE Transactions on Computers TI - An FPGA-based Reconfigurable Mesh Many-Core VL - 63 ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco AU - Meisner, Sebastian ID - 10621 T2 - Reconfigurable Architectures Workshop (RAW) TI - FPGA Redundancy Configurations: An Automated Design Space Exploration ER - TY - GEN AU - Bockhorn, Arne ID - 10627 TI - Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10632 T2 - Proc. MyoElectric Controls Symposium (MEC) TI - A computer vision-based approach to high density EMG pattern recognition using structural similarity ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10633 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity ER - TY - GEN AU - Brand, Marcel ID - 10640 TI - A Generalized Loop Accelerator Implemented as a Coarse-Grained Array ER - TY - GEN AU - Damschen, Marvin ID - 10645 TI - Easy-to-use-on-the-fly binary program acceleration on many-cores ER - TY - CONF AU - Glette, Kyrre AU - Kaufmann, Paul ID - 10654 T2 - IEEE Congress on Evolutionary Computation (CEC) TI - Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System ER - TY - GEN AU - Hagedorn, Christoph ID - 10665 TI - Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10674 KW - Linux KW - hardware-software codesign KW - multiprocessing systems KW - parallel processing KW - LEON3 multicore platform KW - Linux kernel KW - PMU KW - hardware counters KW - hardware-software infrastructure KW - high performance embedded computing KW - perf_event KW - performance monitoring unit KW - Computer architecture KW - Hardware KW - Monitoring KW - Phasor measurement units KW - Radiation detectors KW - Registers KW - Software T2 - 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) TI - A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10677 KW - Linux KW - cache storage KW - embedded systems KW - granular computing KW - multiprocessing systems KW - reconfigurable architectures KW - Leon3 SPARe processor KW - custom logic events KW - evolvable-self-adaptable processor cache KW - fine granular profiling KW - integer unit events KW - measurement infrastructure KW - microarchitectural events KW - multicore embedded system KW - perf_event standard Linux performance measurement interface KW - processor properties KW - run-time reconfigurable memory-to-cache address mapping engine KW - run-time reconfigurable multicore infrastructure KW - split-level caching KW - Field programmable gate arrays KW - Frequency locked loops KW - Irrigation KW - Phasor measurement units KW - Registers KW - Weaving T2 - 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) TI - Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure ER - TY - GEN AU - König, Fabian ID - 10679 TI - EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese ER - TY - GEN AU - Koch, Benjamin ID - 10701 TI - Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA ER - TY - GEN AU - Mittendorf, Robert ID - 10715 TI - Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs ER - TY - GEN AU - Rüthing, Christoph ID - 10732 TI - The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores ER - TY - THES AB - Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go. In this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date. In order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world. We further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches. AU - Schäfers, Lars ID - 10733 SN - 978-3-8325-3748-7 TI - Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go ER - TY - CONF AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10738 T2 - IEEE Power and Energy Society General Meeting (IEEE GM) TI - Optimizing the Generator Start-up Sequence After a Power System Blackout ER - TY - CONF AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10739 T2 - Power Systems Computation Conference (PSCC) TI - A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm ER - TY - GEN AU - Surmund, Sebastian ID - 10744 TI - Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA ER - TY - BOOK AU - I. Esparcia-Alc{\'a}zar, Anna AU - Eiben, A.E. AU - Agapitos, Alexandros AU - Sim{\~o}es, Anabela AU - G.B. Tettamanzi, Andrea AU - Della Cioppa, Antonio AU - M. Mora, Antonio AU - Cotta, Carlos AU - Tarantino, Ernesto AU - Haasdijk, Evert AU - Divina, Federico AU - Fern{\'a}ndez de Vega, Francisco AU - Squillero, Giovanni AU - De Falco, Ivanoe AU - Ignacio Hidalgo, J. AU - Sim, Kevin AU - Glette, Kyrre AU - Zhang, Mengjie AU - Urquhart, Neil AU - Burelli, Paolo AU - Kaufmann, Paul AU - Po{\v s}{\'\i}k, Petr AU - Schaefer, Robert AU - Drechsler, Rolf AU - Antipolis, Sophia AU - Cagnoni, Stefano AU - Thanh Nguyen, Trung AU - S. Bush (editors), William ID - 10756 TI - Applications of Evolutionary Computation - 17th European Conference, EvoApplications VL - 8602 ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10764 T2 - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Yazdani, Majid AU - De Micheli, Giovanni ID - 10773 T2 - 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) TI - Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13154 T2 - 2014 IEEE Conference on Computational Intelligence and Games TI - Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go ER - TY - CHAP AB - Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf. AU - Platzner, Marco AU - Plessl, Christian ED - Künsemöller, Jörn ED - Eke, Norber Otto ED - Foit, Lioba ED - Kaerlein, Timo ID - 335 SN - 978-3-7705-5730-1 T2 - Logiken strukturbildender Prozesse: Automatismen TI - Verschiebungen an der Grenze zwischen Hardware und Software ER - TY - CONF AB - In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. AU - Kenter, Tobias AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 388 T2 - Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC) TI - Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer VL - 8405 ER - TY - JOUR AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices. AU - Agne, Andreas AU - Hangmann, Hendrik AU - Happe, Markus AU - Platzner, Marco AU - Plessl, Christian ID - 363 IS - 8, Part B JF - Microprocessors and Microsystems TI - Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators VL - 38 ER - TY - CONF AB - In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian AU - Sorge, Christoph ID - 377 KW - coldboot T2 - Proceedings of Field-Programmable Custom Computing Machines (FCCM) TI - Reconstructing AES Key Schedules from Decayed Memory with FPGAs ER - TY - JOUR AB - Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 365 IS - 2 JF - ACM Transactions on Reconfigurable Technology and Systems (TRETS) TI - Self-awareness as a Model for Designing and Operating Heterogeneous Multicores VL - 7 ER - TY - JOUR AB - The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications AU - Agne, Andreas AU - Happe, Markus AU - Keller, Ariane AU - Lübbers, Enno AU - Plattner, Bernhard AU - Platzner, Marco AU - Plessl, Christian ID - 328 IS - 1 JF - IEEE Micro TI - ReconOS - An Operating System Approach for Reconfigurable Computing VL - 34 ER - TY - CONF AU - C. Durelli, Gianluca AU - Pogliani, Marcello AU - Miele, Antonio AU - Plessl, Christian AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1778 T2 - Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) TI - Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach ER - TY - CONF AB - Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian ID - 439 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Deferring Accelerator Offloading Decisions to Application Runtime ER - TY - CONF AB - Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 406 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Kernel-Centric Acceleration of High Accuracy Stereo-Matching ER - TY - CONF AU - C. Durelli, Gianluca AU - Copolla, Marcello AU - Djafarian, Karim AU - Koranaros, George AU - Miele, Antonio AU - Paolino, Michele AU - Pell, Oliver AU - Plessl, Christian AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1780 T2 - Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC) TI - SAVE: Towards efficient resource management in heterogeneous system architectures ER - TY - JOUR AU - Giefers, Heiner AU - Plessl, Christian AU - Förstner, Jens ID - 1779 IS - 5 JF - ACM SIGARCH Computer Architecture News KW - funding-maxup KW - tet_topic_hpc SN - 0163-5964 TI - Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers VL - 41 ER - TY - THES AB - Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches. AU - Kaufmann, Paul ID - 11619 SN - 978-3-8325-3530-8 TI - Adapting Hardware Systems by Means of Multi-Objective Evolution ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 1786 T2 - Proc. IEEE Signal Processing and Communications Conf. (SUI) TI - FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm ER - TY - JOUR AU - Kasap, Server AU - Redif, Soydan ID - 1792 IS - 3 JF - IEEE Trans. on Very Large Scale Integration (VLSI) Systems TI - Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices VL - 22 ER - TY - THES AB - Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. AU - Happe, Markus ID - 501 SN - 978-3-8325-3425-7 TI - Performance and thermal management on self-adaptive hybrid multi-cores ER -