Applications of Evolutionary Computation - 20th European Conference, EvoApplications - Squillero, Giovanni; Burelli, Paolo; M. Mora, Antonio; Agapitos, Alexandros; S. Bush, William; Cagnoni, Stefano; Cotta, Carlos; De Falco, Ivanoe; Della Cioppa, Antonio; Divina, Federico; Eiben, A.E.; I. Esparcia-Alcázar, Anna; et al.

Parametrizing Cartesian Genetic Programming: An Empirical Study - Kaufmann, Paul; Kalkreuth, Roman (KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI)

Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches - Kaufmann, Paul; Ho, Nam; Platzner, Marco (Adaptive Hardware and Systems (AHS))

An Empirical Study on the Parametrization of Cartesian Genetic Programming - Kaufmann, Paul; Kalkreuth, Roman (Genetic and Evolutionary Computation (GECCO), Compendium)

Computational self-awareness as design approach for visual sensor nodes - Guettatfi, Zakarya; Hübner, Philipp; Platzner, Marco; Rinner, Bernhard (12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC))
Keywords: embedded systems; image sensors; power aware computing; wireless sensor networks; Zynq-based VSN node prototype; computational self-awareness; design approach; platform levels; power consumption; visual sensor networks; visual sensor nodes; Cameras; Hardware; Middleware; Multicore processing; Operating systems; Runtime; Reconfigurable platforms; distributed embedded systems; performance-resource trade-off; self-awareness; visual sensor nodes

I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems - Ghribi, Ines; Abdallah, Riadh Ben; Khalgui, Mohamed; Platzner, Marco (Communications in Computer and Information Science)

An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip - Wiersema, Tobias; Bockhorn, Arne; Platzner, Marco (Computers & Electrical Engineering)
Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.

FPGA-based acceleration of high density myoelectric signal processing - Boschmann, Alexander; Agne, Andreas; Witschen, Linus; Thombansen, Georg; Kraus, Florian; Platzner, Marco (2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig))

Sprint Diagnostic with RTK-GPS & IMU Sensor Fusion - Cedric Mertens, Jan

Implementation of Bilinear Pairings on Reconfigurable Hardware - Nassery, Abdul Sami

Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method - Amin, Omair

Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs - Anwer, Jahanzeb; Platzner, Marco (Euromicro Conference on Digital System Design (DSD))

A novel immersive augmented reality system for prosthesis training and assessment - Boschmann, Alexander; Dosen, Strahinja; Werner, Andreas; Raies, Ali; Farina, Dario (Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI))

Adaptive playouts for online learning of policies during Monte Carlo Tree Search - Graf, Tobias; Platzner, Marco (Journal Theoretical Computer Science)

Beschleunigte Simulation elektrischer Stromnetze mit GPUs - Horstmann, Jens

Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control - Ma, Chenjie; Kaufmann, Paul; Töbermann, J.-Christian; Braun, Martin (Renewable Energy)

Operating System Support for Reconfigurable Cache - Makeswaran, Vignesh

Private/Shared Data Classification and Implementation for a Multi-Softcore Platform - Ibne Ashraf, Ishraq

Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level - Meisner, Sebastian; Platzner, Marco (Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on)

Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung - Schmidt, Marco

Applications of Evolutionary Computation - 19th European Conference, EvoApplications - Squillero, Giovanni; Burelli, Paolo; M. Mora, Antonio; Agapitos, Alexandros; S. Bush, William; Cagnoni, Stefano; Cotta, Carlos; De Falco, Ivanoe; Della Cioppa, Antonio; Divina, Federico; Eiben, A.E.; I. Esparcia-Alcázar, Anna; et al.

RCo-Design: New Visual Environment for Reconfigurable Embedded Systems - Ghribi, Ines; Ben Abdallah, Riadh; Khalgui, Mohamed; Platzner, Marco (Proceedings of the 30th European Simulation and Modelling Conference (ESM))

New Co-design Methodology for Real-time Embedded Systems - Ghribi, Ines; Ben Abdallah, Riadh; Khalgui, Mohamed; Platzner, Marco (Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA))

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation - Ghasemzadeh Mohammadi, Hassan; Gaillardon, Pierre-Emmanuel; De Micheli, Giovanni (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)

Custom Memory Controller for ReconOS - Hermansen, Sven

Self-aware Computing Systems: An Engineering Approach
Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering.

FPGA-based acceleration of high density myoelectric signal processing - Boschmann, Alexander; Agne, Andreas; Witschen, Linus Matthias; Thombansen, Georg; Kraus, Florian; Platzner, Marco (2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig))
Keywords: Electromyography; Feature extraction; Delays; Hardware Pattern recognition; Prosthetics; High definition video

Using Deep Convolutional Neural Networks in Monte Carlo Tree Search - Graf, Tobias; Platzner, Marco (Computer and Games)

Monte-Carlo Simulation Balancing Revisited - Graf, Tobias; Platzner, Marco (IEEE Computational Intelligence and Games)

Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware - Wiersema, Tobias; Platzner, Marco (Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016))
Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module.

ReconOS - Agne, Andreas; Platzner, Marco; Plessl, Christian; Happe, Markus; Lübbers, Enno (FPGAs for Software Programmers)
In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.

Self-aware Compute Nodes - Agne, Andreas; Happe, Markus; Lösch, Achim; Plessl, Christian; Platzner, Marco (Self-aware Computing Systems)
Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center - Lösch, Achim; Beisel, Tobias; Kenter, Tobias; Plessl, Christian; Platzner, Marco (Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE))
The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.

On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach - Wiersema, Tobias; Wu, Sen; Platzner, Marco (Proceedings of the International Symposium in Reconfigurable Computing (ARC))
Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.

Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten - Knorr, Christoph

Self-Aware and Self-Expressive Systems – Guest Editor's Introduction - Torresen, Jim; Plessl, Christian; Yao, Xin (IEEE Computer)
Keywords: self-awareness; self-expression

Self-Optimizing Organic Cache - Ahmed, Abdullah Fathi

Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing - Beisel, Tobias
The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.

Evolution of Heat Flow Prediction Models for FPGA Devices - Hangmann, Hendrik

Computer Vision basierte Klassifikation von HD EMG Signalen - Haupt, Christian

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings - Ho, Nam; Ahmed, Abdullah Fathi; Kaufmann, Paul; Platzner, Marco (Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS))
Keywords: cache storage; field programmable gate arrays; multiprocessing systems; parallel architectures; reconfigurable architectures; FPGA; dynamic reconfiguration; evolvable cache mapping; many-core architecture; memory-to-cache address mapping function; microarchitectural optimization; multicore architecture; nature-inspired optimization; parallelization degrees; processor; reconfigurable cache mapping; reconfigurable computing; Field programmable gate arrays; Software; Tuning

Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing - Kaufmann, Paul; Shen, Cong (Genetic and Evolutionary Computation (GECCO))

Comparison of thread signatures for error detection in hybrid multi-cores - Meisner, Sebastian; Platzner, Marco (Field Programmable Technology (FPT), 2015 International Conference on)

Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs - Meißner, Roland

Acceleration of Artificial Neural Networks on a Zynq Platform - Posewsky, Thorbjörn

Applications of Evolutionary Computation - 18th European Conference, EvoApplications - M. Mora, Antonio; Squillero, Giovanni; Agapitos, Alexandros; Burelli, Paolo; S. Bush, William; Cagnoni, Stefano; Cotta, Carlos; De Falco, Ivanoe; Della Cioppa, Antonio; Divina, Federico; Eiben, A.E.; I. Esparcia-Alcázar, Anna; et al.

Significant papers from the first 25 years of the FPL conference - H.W. Leong, Philip; Amano, Hideharu; Anderson, Jason; Bertels, Koen; M.P. Cardoso, João; Diessel, Oliver; Gogniat, Guy; Hutton, Mike; Lee, JunKyu; Luk, Wayne; Lysaght, Patrick; Platzner, Marco; et al. (Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL))

New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software - Ghribi, Ines; Ben Abdallah, Riadh; Khalgui, Mohamed; Platzner, Marco (Proceedings of the 29th European Simulation and Modelling Conference (ESM))

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires - Ghasemzadeh Mohammadi, Hassan; Gaillardon, Pierre-Emmanuel; De Micheli, Giovanni (IEEE Transactions on Nanotechnology)

On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors - Ghasemzadeh Mohammadi, Hassan; Gaillardon, Pierre-Emmanuel; Zhang, Jian; De Micheli, Giovanni; Sanchez, Eduardo; Reorda, Matteo Sonza (2015 IEEE Computer Society Annual Symposium on VLSI)

Fault modeling in controllable polarity silicon nanowire circuits - Ghasemzadeh Mohammadi, Hassan; Gaillardon, Pierre-Emmanuel; De Micheli, Giovanni (Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition)

Over effective hard real-time hardware tasks scheduling and allocation - Guettatfi, Zakarya; Kermia, Omar; Khouas, Abdelhakim (25th International Conference on Field Programmable Logic and Applications (FPL))
Keywords: embedded systems; field programmable gate arrays; operating systems (computers); scheduling; μC/OS-II; FPGAs; OS foundation; SafeRTOS; Xenomai; chip utilization ration; complex time constraints; embedded systems; hard real-time hardware task allocation; hard real-time hardware task scheduling; hardware-software real-time operating systems; partially reconfigurable field-programmable gate arrays; resource constraints; safety-critical RTOS; Field programmable gate arrays; Hardware; Job shop scheduling; Real-time systems; Shape; Software

Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning - Graf, Tobias; Platzner, Marco (Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers)

Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study - Kenter, Tobias; Schmitz, Henning; Plessl, Christian (International Journal of Reconfigurable Computing (IJRC))
FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores - Damschen, Marvin; Plessl, Christian (Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT))
This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.

Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm - Schumacher, Jörn; T. Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann-Miotto, Giovanna; Levinson, L.; et al. (Proc. Int. Conf. on Distributed Event-Based Systems (DEBS))

Aktuelles Schlagwort: Approximate Computing - Plessl, Christian; Platzner, Marco; Schreier, Peter J. (Informatik Spektrum)
Keywords: approximate computing; survey

Transparent offloading of computational hotspots from binary code to Xeon Phi - Damschen, Marvin; Riebler, Heinrich; Vaz, Gavin Francis; Plessl, Christian (Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE))
In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.

Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection - Meisner, Sebastian; Platzner, Marco (Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC))
Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead.

On Semeai Detection in Monte-Carlo Go - Graf, Tobias; Schaefers, Lars; Platzner, Marco (Proc. Conf. on Computers and Games (CG))

Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring - Wiersema, Tobias; Drzevitzky, Stephanie; Platzner, Marco (Proceedings of the International Conference on Field-Programmable Technology (FPT))
Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric.

Integrating Software and Hardware Verification - Jakobs, Marie-Christine; Platzner, Marco; Wiersema, Tobias; Wehrheim, Heike (Proceedings of the 11th International Conference on Integrated Formal Methods (iFM))
Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques.

Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA - Wiersema, Tobias; Bockhorn, Arne; Platzner, Marco (Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig))
Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.

A Novel Technique and its Application to Computer Go - Schaefers, Lars; Platzner, Marco (IEEE Transactions on Computational Intelligence and AI in Games)

An FPGA-based Reconfigurable Mesh Many-Core - Giefers, Heiner; Platzner, Marco (IEEE Transactions on Computers)

FPGA Redundancy Configurations: An Automated Design Space Exploration - Anwer, Jahanzeb; Platzner, Marco; Meisner, Sebastian (Reconfigurable Architectures Workshop (RAW))

Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board - Bockhorn, Arne

A computer vision-based approach to high density EMG pattern recognition using structural similarity - Boschmann, Alexander; Platzner, Marco (Proc. MyoElectric Controls Symposium (MEC))

Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity - Boschmann, Alexander; Platzner, Marco (Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC))

A Generalized Loop Accelerator Implemented as a Coarse-Grained Array - Brand, Marcel

Easy-to-use-on-the-fly binary program acceleration on many-cores - Damschen, Marvin

Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System - Glette, Kyrre; Kaufmann, Paul (IEEE Congress on Evolutionary Computation (CEC))

Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten - Hagedorn, Christoph

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms - Ho, Nam; Kaufmann, Paul; Platzner, Marco (24th Intl. Conf. on Field Programmable Logic and Applications (FPL))
Keywords: Linux; hardware-software codesign; multiprocessing systems; parallel processing; LEON3 multicore platform; Linux kernel; PMU; hardware counters; hardware-software infrastructure; high performance embedded computing; perf_event; performance monitoring unit; Computer architecture; Hardware; Monitoring; Phasor measurement units; Radiation detectors; Registers; Software

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure - Ho, Nam; Kaufmann, Paul; Platzner, Marco (2014 IEEE Intl. Conf. on Evolvable Systems (ICES))
Keywords: Linux; cache storage; embedded systems; granular computing; multiprocessing systems; reconfigurable architectures; Leon3 SPARe processor; custom logic events; evolvable-self-adaptable processor cache; fine granular profiling; integer unit events; measurement infrastructure; microarchitectural events; multicore embedded system; perf_event standard Linux performance measurement interface; processor properties; run-time reconfigurable memory-to-cache address mapping engine; run-time reconfigurable multicore infrastructure; split-level caching; Field programmable gate arrays; Frequency locked loops; Irrigation; Phasor measurement units; Registers; Weaving

EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese - König, Fabian

Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA - Koch, Benjamin

Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs - Mittendorf, Robert

The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores - Rüthing, Christoph

Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go - Schäfers, Lars
Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go. In this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date. In order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world. We further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.

Optimizing the Generator Start-up Sequence After a Power System Blackout - Shen, Cong; Kaufmann, Paul; Braun, Martin (IEEE Power and Energy Society General Meeting (IEEE GM))

A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm - Shen, Cong; Kaufmann, Paul; Braun, Martin (Power Systems Computation Conference (PSCC))

Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA - Surmund, Sebastian

Applications of Evolutionary Computation - 17th European Conference, EvoApplications - I. Esparcia-Alcázar, Anna; Eiben, A.E.; Agapitos, Alexandros; Simões, Anabela; G.B. Tettamanzi, Andrea; Della Cioppa, Antonio; M. Mora, Antonio; Cotta, Carlos; Tarantino, Ernesto; Haasdijk, Evert; Divina, Federico; Fernández de Vega, Francisco; et al.

Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs - Anwer, Jahanzeb; Platzner, Marco (IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT))

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection - Ghasemzadeh Mohammadi, Hassan; Gaillardon, Pierre-Emmanuel; Yazdani, Majid; De Micheli, Giovanni (2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH))

Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go - Graf, Tobias; Platzner, Marco (2014 IEEE Conference on Computational Intelligence and Games)

Verschiebungen an der Grenze zwischen Hardware und Software - Platzner, Marco; Plessl, Christian (Logiken strukturbildender Prozesse: Automatismen)
Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinﬂusst und sogar zur Entstehung von neuen Forschungsrichtungen geführt. In diesem Beitrag beschäftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenständige Produkte diﬀerenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, geführt hat. Im Hardware/Software Co-design ﬁndet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software während der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen können wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom während der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonﬁgurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers während der Laufzeit verändert werden kann. Diese Technologie führt zu einer durchlässigen Grenze zwischen Hardware und Software bzw. löst sie die herkömmliche Vorstellung einer festen Hardware und einer ﬂexiblen Software damit auf.

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer - Kenter, Tobias; Vaz, Gavin Francis; Plessl, Christian (Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC))
In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.

Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators - Agne, Andreas; Hangmann, Hendrik; Happe, Markus; Platzner, Marco; Plessl, Christian (Microprocessors and Microsystems)
Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.

Reconstructing AES Key Schedules from Decayed Memory with FPGAs - Riebler, Heinrich; Kenter, Tobias; Plessl, Christian; Sorge, Christoph (Proceedings of Field-Programmable Custom Computing Machines (FCCM))
In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.
Keywords: coldboot

Self-awareness as a Model for Designing and Operating Heterogeneous Multicores - Agne, Andreas; Happe, Markus; Lösch, Achim; Plessl, Christian; Platzner, Marco (ACM Transactions on Reconfigurable Technology and Systems (TRETS))
Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.

ReconOS - An Operating System Approach for Reconfigurable Computing - Agne, Andreas; Happe, Markus; Keller, Ariane; Lübbers, Enno; Plattner, Bernhard; Platzner, Marco; Plessl, Christian (IEEE Micro)
The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach - C. Durelli, Gianluca; Pogliani, Marcello; Miele, Antonio; Plessl, Christian; Riebler, Heinrich; Vaz, Gavin Francis; D. Santambrogio, Marco; Bolchini, Cristiana (Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA))

Deferring Accelerator Offloading Decisions to Application Runtime - Vaz, Gavin Francis; Riebler, Heinrich; Kenter, Tobias; Plessl, Christian (Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig))
Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.

Kernel-Centric Acceleration of High Accuracy Stereo-Matching - Kenter, Tobias; Schmitz, Henning; Plessl, Christian (Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig))
Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.

SAVE: Towards efficient resource management in heterogeneous system architectures - C. Durelli, Gianluca; Copolla, Marcello; Djafarian, Karim; Koranaros, George; Miele, Antonio; Paolino, Michele; Pell, Oliver; Plessl, Christian; D. Santambrogio, Marco; Bolchini, Cristiana (Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC))

Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers - Giefers, Heiner; Plessl, Christian; Förstner, Jens (ACM SIGARCH Computer Architecture News)
Keywords: funding-maxup; tet_topic_hpc

Adapting Hardware Systems by Means of Multi-Objective Evolution - Kaufmann, Paul
Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.

FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm - Kasap, Server; Redif, Soydan (Proc. IEEE Signal Processing and Communications Conf. (SUI))