TY - GEN AU - Hagedorn, Christoph ID - 10665 TI - Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10674 KW - Linux KW - hardware-software codesign KW - multiprocessing systems KW - parallel processing KW - LEON3 multicore platform KW - Linux kernel KW - PMU KW - hardware counters KW - hardware-software infrastructure KW - high performance embedded computing KW - perf_event KW - performance monitoring unit KW - Computer architecture KW - Hardware KW - Monitoring KW - Phasor measurement units KW - Radiation detectors KW - Registers KW - Software T2 - 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) TI - A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10677 KW - Linux KW - cache storage KW - embedded systems KW - granular computing KW - multiprocessing systems KW - reconfigurable architectures KW - Leon3 SPARe processor KW - custom logic events KW - evolvable-self-adaptable processor cache KW - fine granular profiling KW - integer unit events KW - measurement infrastructure KW - microarchitectural events KW - multicore embedded system KW - perf_event standard Linux performance measurement interface KW - processor properties KW - run-time reconfigurable memory-to-cache address mapping engine KW - run-time reconfigurable multicore infrastructure KW - split-level caching KW - Field programmable gate arrays KW - Frequency locked loops KW - Irrigation KW - Phasor measurement units KW - Registers KW - Weaving T2 - 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) TI - Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure ER - TY - GEN AU - König, Fabian ID - 10679 TI - EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese ER - TY - GEN AU - Koch, Benjamin ID - 10701 TI - Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA ER - TY - GEN AU - Mittendorf, Robert ID - 10715 TI - Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs ER - TY - GEN AU - Rüthing, Christoph ID - 10732 TI - The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores ER - TY - THES AB - Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go. In this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date. In order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world. We further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches. AU - Schäfers, Lars ID - 10733 SN - 978-3-8325-3748-7 TI - Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go ER - TY - CONF AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10738 T2 - IEEE Power and Energy Society General Meeting (IEEE GM) TI - Optimizing the Generator Start-up Sequence After a Power System Blackout ER - TY - CONF AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10739 T2 - Power Systems Computation Conference (PSCC) TI - A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm ER - TY - GEN AU - Surmund, Sebastian ID - 10744 TI - Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA ER - TY - BOOK AU - I. Esparcia-Alc{\'a}zar, Anna AU - Eiben, A.E. AU - Agapitos, Alexandros AU - Sim{\~o}es, Anabela AU - G.B. Tettamanzi, Andrea AU - Della Cioppa, Antonio AU - M. Mora, Antonio AU - Cotta, Carlos AU - Tarantino, Ernesto AU - Haasdijk, Evert AU - Divina, Federico AU - Fern{\'a}ndez de Vega, Francisco AU - Squillero, Giovanni AU - De Falco, Ivanoe AU - Ignacio Hidalgo, J. AU - Sim, Kevin AU - Glette, Kyrre AU - Zhang, Mengjie AU - Urquhart, Neil AU - Burelli, Paolo AU - Kaufmann, Paul AU - Po{\v s}{\'\i}k, Petr AU - Schaefer, Robert AU - Drechsler, Rolf AU - Antipolis, Sophia AU - Cagnoni, Stefano AU - Thanh Nguyen, Trung AU - S. Bush (editors), William ID - 10756 TI - Applications of Evolutionary Computation - 17th European Conference, EvoApplications VL - 8602 ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10764 T2 - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Yazdani, Majid AU - De Micheli, Giovanni ID - 10773 T2 - 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) TI - Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13154 T2 - 2014 IEEE Conference on Computational Intelligence and Games TI - Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go ER - TY - CHAP AB - Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf. AU - Platzner, Marco AU - Plessl, Christian ED - Künsemöller, Jörn ED - Eke, Norber Otto ED - Foit, Lioba ED - Kaerlein, Timo ID - 335 SN - 978-3-7705-5730-1 T2 - Logiken strukturbildender Prozesse: Automatismen TI - Verschiebungen an der Grenze zwischen Hardware und Software ER - TY - CONF AB - In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. AU - Kenter, Tobias AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 388 T2 - Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC) TI - Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer VL - 8405 ER - TY - JOUR AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices. AU - Agne, Andreas AU - Hangmann, Hendrik AU - Happe, Markus AU - Platzner, Marco AU - Plessl, Christian ID - 363 IS - 8, Part B JF - Microprocessors and Microsystems TI - Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators VL - 38 ER - TY - CONF AB - In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian AU - Sorge, Christoph ID - 377 KW - coldboot T2 - Proceedings of Field-Programmable Custom Computing Machines (FCCM) TI - Reconstructing AES Key Schedules from Decayed Memory with FPGAs ER - TY - JOUR AB - Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 365 IS - 2 JF - ACM Transactions on Reconfigurable Technology and Systems (TRETS) TI - Self-awareness as a Model for Designing and Operating Heterogeneous Multicores VL - 7 ER - TY - JOUR AB - The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications AU - Agne, Andreas AU - Happe, Markus AU - Keller, Ariane AU - Lübbers, Enno AU - Plattner, Bernhard AU - Platzner, Marco AU - Plessl, Christian ID - 328 IS - 1 JF - IEEE Micro TI - ReconOS - An Operating System Approach for Reconfigurable Computing VL - 34 ER - TY - CONF AU - C. Durelli, Gianluca AU - Pogliani, Marcello AU - Miele, Antonio AU - Plessl, Christian AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1778 T2 - Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) TI - Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach ER - TY - CONF AB - Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian ID - 439 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Deferring Accelerator Offloading Decisions to Application Runtime ER - TY - CONF AB - Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 406 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Kernel-Centric Acceleration of High Accuracy Stereo-Matching ER - TY - CONF AU - C. Durelli, Gianluca AU - Copolla, Marcello AU - Djafarian, Karim AU - Koranaros, George AU - Miele, Antonio AU - Paolino, Michele AU - Pell, Oliver AU - Plessl, Christian AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1780 T2 - Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC) TI - SAVE: Towards efficient resource management in heterogeneous system architectures ER - TY - JOUR AU - Giefers, Heiner AU - Plessl, Christian AU - Förstner, Jens ID - 1779 IS - 5 JF - ACM SIGARCH Computer Architecture News KW - funding-maxup KW - tet_topic_hpc SN - 0163-5964 TI - Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers VL - 41 ER - TY - THES AB - Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches. AU - Kaufmann, Paul ID - 11619 SN - 978-3-8325-3530-8 TI - Adapting Hardware Systems by Means of Multi-Objective Evolution ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 1786 T2 - Proc. IEEE Signal Processing and Communications Conf. (SUI) TI - FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm ER - TY - JOUR AU - Kasap, Server AU - Redif, Soydan ID - 1792 IS - 3 JF - IEEE Trans. on Very Large Scale Integration (VLSI) Systems TI - Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices VL - 22 ER - TY - THES AB - Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. AU - Happe, Markus ID - 501 SN - 978-3-8325-3425-7 TI - Performance and thermal management on self-adaptive hybrid multi-cores ER - TY - JOUR AU - Happe, Markus AU - Lübbers, Enno AU - Platzner, Marco ID - 10604 IS - 1 JF - International Journal of Real-time Image Processing TI - A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking VL - 8 ER - TY - CONF AU - Anwer, Jahanzeb AU - Meisner, Sebastian AU - Platzner, Marco ID - 10620 KW - fault tolerant computing KW - field programmable gate arrays KW - logic design KW - reliability KW - BYU-LANL tool KW - DRM tool flow KW - FPGA based hardware designs KW - avionic application KW - device technologies KW - dynamic reliability management KW - fault-tolerant operation KW - hardware designs KW - reconfiguring reliability levels KW - space applications KW - Field programmable gate arrays KW - Hardware KW - Redundancy KW - Reliability engineering KW - Runtime KW - Tunneling magnetoresistance T2 - Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on TI - Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime ER - TY - GEN AU - Bick, Christian ID - 10626 TI - Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner ER - TY - CONF AU - Boschmann, Alexander AU - Nofen, Barbara AU - Platzner, Marco ID - 10634 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10635 T2 - Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC) TI - Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array ER - TY - CONF AU - Glette, Kyrre AU - Kaufmann, Paul AU - Assad, Christopher AU - Wolf, Michael ID - 10655 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface VL - 1 ER - TY - BOOK AU - Kaufmann, Paul ID - 10681 TI - Adapting Hardware Systems by Means of Multi-Objective Evolution ER - TY - JOUR AU - Kaufmann, Paul AU - Glette, Kyrre AU - Gruber, Tiemo AU - Platzner, Marco AU - Torresen, Jim AU - Sick, Bernhard ID - 10684 IS - 1 JF - IEEE Transactions on Evolutionary Computation TI - Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers VL - 17 ER - TY - GEN AU - Knoop, Michael ID - 10700 TI - Behavior Models for Electric Vehicles ER - TY - GEN AU - Nofen, Barbara ID - 10720 TI - Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors ER - TY - GEN AU - Pudelko, Daniel ID - 10727 TI - Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs ER - TY - GEN AU - Riebler, Heinrich ID - 10730 TI - Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs ER - TY - GEN AU - Sprenger, Alexander ID - 10741 TI - MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung ER - TY - GEN AU - Steppeler, Philipp ID - 10743 TI - Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen ER - TY - CONF AU - Toebermann, Christian AU - Geibel, Daniel AU - Hau, Manuel AU - Brandl, Ron AU - Kaufmann, Paul AU - Ma, Chenjie AU - Braun, Martin AU - Degner, Tobias ID - 10745 T2 - Real-Time Conference TI - Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Yazdani, Majid AU - De Micheli, Giovanni ID - 10774 T2 - 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) TI - A fast TCAD-based methodology for Variation analysis of emerging nano-devices ER - TY - CONF AU - Gaillardon, Pierre-Emmanuel AU - Ghasemzadeh Mohammadi, Hassan AU - De Micheli, Giovanni ID - 10775 T2 - 2013 14th Latin American Test Workshop-LATW TI - Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study ER - TY - CONF AU - Graf, Tobias AU - Schäfers, Lars AU - Platzner, Marco ID - 13645 T2 - Proceedings of the International Conference on Computers and Games (CG) TI - On Semeai Detection in Monte-Carlo Go. ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - JOUR AU - Thielemans, Kris AU - Tsoumpas, Charalampos AU - Mustafovic, Sanida AU - Beisel, Tobias AU - Aguiar, Pablo AU - Dikaios, Nikolaos AU - W Jacobson, Matthew ID - 2172 IS - 4 JF - Physics in Medicine and Biology TI - STIR: Software for Tomographic Image Reconstruction Release 2 VL - 57 ER - TY - JOUR AU - Redif, Soydan AU - Kasap, Server ID - 2173 IS - 12 JF - Int. Journal of Electronics TI - Parallel algorithm for computation of second-order sequential best rotations VL - 100 ER - TY - JOUR AU - Kasap, Server AU - Benkrid, Khaled ID - 2174 IS - 6 JF - Journal of Computers TI - Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer VL - 7 ER - TY - THES AB - FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety. AU - Drzevitzky, Stephanie ID - 586 TI - Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security ER - TY - GEN AU - Plessl, Christian AU - Platzner, Marco AU - Agne, Andreas AU - Happe, Markus AU - Lübbers, Enno ID - 587 TI - Programming models for reconfigurable heterogeneous multi-cores ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10636 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array ER - TY - GEN AU - Dridger, Denis ID - 10650 TI - Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer ER - TY - THES AB - The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores. The book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores. AU - Giefers, Heiner ID - 10652 SN - 978-3-8325-3165-2 TI - Design and Programming of Reconfigurable Mesh based Many-Cores ER - TY - GEN AU - Graf, Tobias ID - 10658 TI - Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go ER - TY - GEN AU - Hangmann, Hendrik ID - 10667 TI - Generating Adjustable Temperature Gradients on modern FPGAs ER - TY - JOUR AU - Kaufmann, Paul AU - Glette, Kyrre AU - Platzner, Marco AU - Torresen, Jim ID - 10685 IS - 4 JF - International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) TI - Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture VL - 3 ER - TY - GEN AU - Platzner, Marco AU - Boschmann, Alexander AU - Kaufmann, Paul ID - 10723 TI - Wieder natürlich gehen und greifen ER - TY - GEN AU - Schmitz, Henning ID - 10734 TI - Stereo Matching on a HC-1 Hybrid Core Computer ER - TY - GEN AU - Topmöller, Christoph ID - 10747 TI - Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System ER - TY - GEN AU - Wistuba, Martin ID - 10754 TI - Analysis of Pattern Based Model Design and Learning in Computer-Go ER - TY - GEN AU - Lewis, Peter AU - Platzner, Marco AU - Yao, Xin ID - 13462 TI - An outlook for self-awareness in computing systems ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - JOUR AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2108 IS - 2 JF - Microprocessors and Microsystems KW - funding-altera SN - 0141-9331 TI - IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators VL - 36 ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - JOUR AU - Grad, Mariusz AU - Plessl, Christian ID - 2177 JF - Int. Journal of Reconfigurable Computing (IJRC) TI - On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CHAP AU - Plessl, Christian AU - Platzner, Marco ED - Khalgui, Mohamed ED - Hanisch, Hans-Michael ID - 2202 SN - 978-1-60960-086-0 T2 - Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility TI - Hardware Virtualization on Dynamically Reconfigurable Embedded Processors ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AB - Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach. AU - Drzevitzky, Stephanie AU - Platzner, Marco ID - 666 T2 - Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco ID - 10637 T2 - Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT) TI - Accurate gait phase detection using surface electromyographic signals and support vector machines ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco AU - Robrecht, Michael AU - Hahn, Martin AU - Winkler, Michael ID - 10638 T2 - Proc. MyoElectric Controls Symposium (MEC) TI - Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems ER - TY - GEN AU - Ikonomakis, Nikolaos ID - 10678 TI - PinSim: Schnelle Simulation mit Pintools ER - TY - GEN AU - Kassner, Hendrik ID - 10680 TI - MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern ER - TY - CHAP AU - Kaufmann, Paul AU - Platzner, Marco ED - Müller-Schloer, Christian ED - Schmeck, Hartmut ED - Ungerer, Theo ID - 10687 T2 - Organic Computing---A Paradigm Shift for Complex Systems TI - Multi-objective Intrinsic Evolution of Embedded Systems VL - 1 ER - TY - GEN AU - Schwabe, Arne ID - 10736 TI - Analysis of Algorithmic Approaches for Temporal Partitioning ER - TY - CHAP AU - Sekanina, Lukas AU - Walker, James Alfred AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 10737 T2 - Cartesian Genetic Programming TI - Evolution of Electronic Circuits ER - TY - CHAP AU - Walker, James Alfred AU - Miller, Julian F. AU - Kaufmann, Paul AU - Platzner, Marco ID - 10748 T2 - Cartesian Genetic Programming TI - Problem Decomposition in Cartesian Genetic Programming ER - TY - GEN AU - Welp, Daniel ID - 10750 TI - User Space Scheduling for Heterogeneous Systems ER - TY - CONF AU - Agne, Andreas AU - Platzner, Marco AU - Lübbers, Enno ID - 13643 SN - 9781457714849 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Memory Virtualization for Multithreaded Reconfigurable Hardware ER - TY - CONF AU - Henkel, Jörg AU - Hedrich, Lars AU - Herkersdorf, Andreas AU - Kapitza, Rüdiger AU - Lohmann, Daniel AU - Marwedel, Peter AU - Platzner, Marco AU - Rosenstiel, Wolfgang AU - Schlichtmann, Ulf AU - Spinczyk, Olaf AU - Tahoori, Mehdi AU - Bauer, Lars AU - Teich, Jürgen AU - Wehn, Norbert AU - Wunderlich, Hans-Joachim AU - Becker, Joachim AU - Bringmann, Oliver AU - Brinkschulte, Uwe AU - Chakraborty, Samarjit AU - Engel, Michael AU - Ernst, Rolf AU - Härtig, Hermann ID - 13644 SN - 9781450307154 T2 - Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11 TI - Design and architectures for dependable embedded systems ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - JOUR AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2201 JF - Int. Journal of Recon- figurable Computing (IJRC) KW - funding-altera TI - FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER -