TY - CHAP AU - Plessl, Christian AU - Platzner, Marco ED - Khalgui, Mohamed ED - Hanisch, Hans-Michael ID - 2202 SN - 978-1-60960-086-0 T2 - Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility TI - Hardware Virtualization on Dynamically Reconfigurable Embedded Processors ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AB - Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach. AU - Drzevitzky, Stephanie AU - Platzner, Marco ID - 666 T2 - Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco ID - 10637 T2 - Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT) TI - Accurate gait phase detection using surface electromyographic signals and support vector machines ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco AU - Robrecht, Michael AU - Hahn, Martin AU - Winkler, Michael ID - 10638 T2 - Proc. MyoElectric Controls Symposium (MEC) TI - Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems ER - TY - GEN AU - Ikonomakis, Nikolaos ID - 10678 TI - PinSim: Schnelle Simulation mit Pintools ER - TY - GEN AU - Kassner, Hendrik ID - 10680 TI - MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern ER - TY - CHAP AU - Kaufmann, Paul AU - Platzner, Marco ED - Müller-Schloer, Christian ED - Schmeck, Hartmut ED - Ungerer, Theo ID - 10687 T2 - Organic Computing---A Paradigm Shift for Complex Systems TI - Multi-objective Intrinsic Evolution of Embedded Systems VL - 1 ER - TY - GEN AU - Schwabe, Arne ID - 10736 TI - Analysis of Algorithmic Approaches for Temporal Partitioning ER - TY - CHAP AU - Sekanina, Lukas AU - Walker, James Alfred AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 10737 T2 - Cartesian Genetic Programming TI - Evolution of Electronic Circuits ER - TY - CHAP AU - Walker, James Alfred AU - Miller, Julian F. AU - Kaufmann, Paul AU - Platzner, Marco ID - 10748 T2 - Cartesian Genetic Programming TI - Problem Decomposition in Cartesian Genetic Programming ER - TY - GEN AU - Welp, Daniel ID - 10750 TI - User Space Scheduling for Heterogeneous Systems ER - TY - CONF AU - Agne, Andreas AU - Platzner, Marco AU - Lübbers, Enno ID - 13643 SN - 9781457714849 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Memory Virtualization for Multithreaded Reconfigurable Hardware ER - TY - CONF AU - Henkel, Jörg AU - Hedrich, Lars AU - Herkersdorf, Andreas AU - Kapitza, Rüdiger AU - Lohmann, Daniel AU - Marwedel, Peter AU - Platzner, Marco AU - Rosenstiel, Wolfgang AU - Schlichtmann, Ulf AU - Spinczyk, Olaf AU - Tahoori, Mehdi AU - Bauer, Lars AU - Teich, Jürgen AU - Wehn, Norbert AU - Wunderlich, Hans-Joachim AU - Becker, Joachim AU - Bringmann, Oliver AU - Brinkschulte, Uwe AU - Chakraborty, Samarjit AU - Engel, Michael AU - Ernst, Rolf AU - Härtig, Hermann ID - 13644 SN - 9781450307154 T2 - Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11 TI - Design and architectures for dependable embedded systems ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - JOUR AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2201 JF - Int. Journal of Recon- figurable Computing (IJRC) KW - funding-altera TI - FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - JOUR AU - Drzevitzky, Stephanie AU - Kastens, Uwe AU - Platzner, Marco ID - 10605 JF - International Journal of Reconfigurable Computing TI - Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification VL - 2010 ER - TY - GEN AU - Agne, Andreas ID - 10614 TI - Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen ER - TY - GEN AU - Boschmann, Alexander ID - 10629 TI - EMG-basierte Ganganalyse ER - TY - GEN AU - Breitlauch, Daniel ID - 10642 TI - Evolvable Cache Controller ER - TY - GEN AU - Dridger, Denis ID - 10649 TI - Soft Microprocessors with tightly coupled Application-Specific Coprocessors ER - TY - GEN AU - Graf, Tobias ID - 10657 TI - Parallelization of the UCT Algorithm on HPC-Clusters ER - TY - CONF AU - Kaufmann, Paul AU - Englehart, Kevin AU - Platzner, Marco ID - 10683 T2 - International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) TI - Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms ER - TY - CONF AU - Kaufmann, Paul AU - Knieper, Tobias AU - Platzner, Marco ID - 10686 T2 - IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) TI - A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers ER - TY - JOUR AU - Kebschull, Udo AU - Platzner, Marco AU - Teich, Jürgen ID - 10694 IS - 3 JF - IET Computers Digital Techniques SN - 1751-8601 TI - Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial) VL - 4 ER - TY - GEN AU - Knieper, Tobias ID - 10697 TI - Hybridization of Global Multi-Objective and Local Search Techniques ER - TY - CONF AU - Knieper, Tobias AU - Kaufmann, Paul AU - Glette, Kyrre AU - Platzner, Marco AU - Torresen, Jim ID - 10699 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture VL - 6274 ER - TY - CHAP AU - Lübbers, Enno AU - Platzner, Marco ED - Platzner, Marco ED - Teich, Jürgen ED - Wehn, Norbert ID - 10704 T2 - Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications TI - ReconOS: An Operating System for Dynamically Reconfigurable Hardware ER - TY - GEN AU - Meiche, Robert ID - 10710 TI - FPGA/CPU Multicore-Plattform für ReconOS/eCos ER - TY - GEN AU - Niekamp, Manuel ID - 10717 TI - Transparente Hardwarebeschleunigung durch Shared Library Interposing ER - TY - GEN AU - Runde, Bodo ID - 10731 TI - A Token-Ring Network-On-Chip for Message Passing in ReconOS ER - TY - GEN AU - Wiersema, Tobias ID - 10752 TI - Scheduling Support for Heterogeneous Hardware Accelerators under Linux ER - TY - BOOK ED - Platzner, Marco ED - Teich, Jürgen ED - Wehn, Norbert ID - 10763 SN - 9048134846 TI - Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications ER - TY - CONF AU - Khatir, Mehrdad AU - Ghasemzadeh Mohammadi, Hassan AU - Ejlali, Alireza ID - 10776 T2 - Computer Design (ICCD), 2010 IEEE International Conference on TI - Sub-threshold charge recovery circuits ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13640 T2 - Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL) TI - A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier ER - TY - CONF AU - Schäfer, Wilhelm AU - Birattari, Mauro AU - Blömer, Johannes AU - Dorigo, Marco AU - Engels, Gregor AU - O'Grady, Rehan AU - Platzner, Marco AU - Rammig, Franz-Josef AU - Reif, Wolfgang AU - Trächtler, Ansgar ID - 13641 T2 - Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER) TI - Engineering Self-Coordinating Software Intensive Systems ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13642 T2 - Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian AU - Keller, Ariane AU - Plattner, Bernhard ID - 2223 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - GEN ED - Plaks, Toomas P. ED - Andrews, David ED - DeMara, Ronald ED - Lam, Herman ED - Lee, Jooheung ED - Plessl, Christian ED - Stitt, Greg ID - 2222 SN - 1-60132-140-6 TI - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) ER - TY - CONF AU - Beisel, Tobias AU - Niekamp, Manuel AU - Plessl, Christian ID - 2226 SN - 978-1-4244-6965-9 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco AU - Winkler, Michael ID - 10639 T2 - Proc. Technically Assisted Rehabilitation (TAR) TI - Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets ER - TY - GEN AU - Kostin, Alexander ID - 10702 TI - Evolvable Robot Controller ER - TY - JOUR AU - Lübbers, Enno AU - Platzner, Marco ID - 10703 IS - 1 JF - ACM Transactions on Embedded Computing Systems KW - Reconfigurable computing KW - multithreading KW - operating systems SN - 1539-9087 TI - ReconOS: Multithreaded Programming for Reconfigurable Computers VL - 9 ER - TY - GEN AU - Tofall, Martin ID - 10746 TI - Compiler for a Custom Instruction Set CPU ER - TY - GEN AU - Warkentin, Alexander ID - 10749 TI - Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units ER - TY - GEN AU - Wildenhain, Benedikt ID - 10753 TI - Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Miremadi, Seyed Ghassem AU - Ejlali, Alireza ID - 10777 T2 - Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on TI - Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors ER - TY - CONF AU - Happe, Markus AU - Lübbers, Enno AU - Platzner, Marco ID - 13632 T2 - Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC) TI - A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13634 T2 - Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS) TI - Towards Models for Many-Cores: The Case for the Reconfigurable Mesh ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13635 T2 - Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium TI - ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13636 T2 - Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) TI - Cooperative Multithreading in Dynamically Reconfigurable Systems ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13637 T2 - Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) TI - Program-driven Fine-grained Power Management for the Reconfigurable Mesh ER - TY - CONF AU - Happe, Markus AU - Lübbers, Enno AU - Platzner, Marco ID - 13638 SN - 9781424443758 T2 - Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT) TI - An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning ER - TY - CONF AU - Drzevitzky, Stephanie AU - Kastens, Uwe AU - Platzner, Marco ID - 13639 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules ER - TY - CONF AB - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2350 KW - IMORC KW - interconnect KW - performance SN - 978-1-4244-4450-2 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing ER - TY - CONF AB - In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 2262 KW - EvoCache KW - evolvable hardware KW - computer architecture T2 - Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) TI - EvoCaches: Application-specific Adaptation of Cache Mapping ER - TY - CONF AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2238 KW - IMORC KW - graphics SN - 978-0-7695-3917-1 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2261 KW - IMORC KW - NOC KW - KNN KW - accelerator SN - 1946-1488 T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure ER - TY - CONF AB - In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. AU - Grad, Mariusz AU - Plessl, Christian ID - 2263 SN - 1-60132-101-5 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX ER - TY - CONF AU - Beisel, Tobias AU - Lietsch, Stefan AU - Thielemans, Kris ID - 2358 T2 - IEEE Nuclear Science Symposium Conference Record (NSS) TI - A method for OSEM PET reconstruction on parallel architectures using STIR ER - TY - CONF AU - Platzner, Marco AU - Döhre, Sven AU - Happe, Markus AU - Kenter, Tobias AU - Lorenz, Ulf AU - Schumacher, Tobias AU - Send, Andre AU - Warkentin, Alexander ID - 2365 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - The GOmputer: Accelerating GO with FPGAs ER - TY - GEN AU - Boschmann, Alexander ID - 10628 TI - Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen ER - TY - GEN AU - Breitlauch, Daniel ID - 10641 TI - Selbstoptimierender Cache-Kontroller ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10644 TI - Verteilte Simulation von mobilen Robotern mit EyeSim ER - TY - CONF AU - Glette, Kyrre AU - Gruber, Thiemo AU - Kaufmann, Paul AU - Torresen, Jim AU - Sick, Bernhard AU - Platzner, Marco ID - 10653 T2 - IEEE Adaptive Hardware and Systems (AHS) TI - Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control ER - TY - CONF AU - Glette, Kyrre AU - Torresen, Jim AU - Kaufmann, Paul AU - Platzner, Marco ID - 10656 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - A Comparison of Evolvable Hardware Architectures for Classification Tasks VL - 5216 ER - TY - GEN AU - Happe, Markus ID - 10669 TI - Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern ER - TY - GEN AU - Torresen, Jim AU - Glette, Kyrre AU - Platzner, Marco AU - Kaufmann, Paul ID - 10690 TI - Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS) ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10691 T2 - Genetic and Evolutionary Computation (GECCO) TI - Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming ER - TY - GEN AU - Knieper, Tobias ID - 10696 TI - Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf ER - TY - CONF AU - Knieper, Tobias AU - Defo, Bertrand AU - Kaufmann, Paul AU - Platzner, Marco ID - 10698 T2 - Biologically Inspired Collaborative Computing (BICC) TI - On Robust Evolution of Digital Hardware VL - 268 ER - TY - GEN AU - Niklas, Jörg ID - 10718 TI - Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme ER - TY - GEN AU - Östermann, Marco ID - 10721 TI - Raytracing on a Custom Instruction Set CPU ER - TY - GEN AU - Westerheide, Nico ID - 10751 TI - Design and Evaluation of MicroBlaze Multi-core Architectures ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Tabkhi, Hamed AU - Miremadi, Seyed Ghassem AU - Ejlali, Alireza ID - 10778 T2 - 2008 International Conference on Microelectronics TI - A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13629 T2 - Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS) TI - Realizing Reconfigurable Mesh Algorithms on Softcore Arrays ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13630 T2 - Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Communication and Synchronization in Multithreaded Reconfigurable Computing Systems ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13631 SN - 9781424419609 T2 - Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL) TI - A portable abstraction layer for hardware threads ER - TY - CONF AU - Schumacher, Tobias AU - Meiche, Robert AU - Kaufmann, Paul AU - Lübbers, Enno AU - Plessl, Christian AU - Platzner, Marco ID - 2364 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Hardware Accelerator for k-th Nearest Neighbor Thinning ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2372 KW - IMORC KW - IP core KW - interconnect T2 - Many-core and Reconfigurable Supercomputing Conference (MRSC) TI - IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers ER - TY - CONF AB - In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits. AU - Kaufmann, Paul AU - Platzner, Marco ID - 6508 KW - integrated circuit design KW - hardware evolution KW - evolutionary hardware design KW - evolutionary optimizers KW - hash functions KW - preengineered circuits KW - Hardware KW - Circuits KW - Design optimization KW - Visualization KW - Genetic programming KW - Genetic mutations KW - Clustering algorithms KW - Biological cells KW - Field programmable gate arrays KW - Routing SN - 076952866X T2 - Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) TI - MOVES: A Modular Framework for Hardware Evolution ER - TY - GEN AU - Beisel, Tobias ID - 10623 TI - Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen ER - TY - JOUR AU - Bergmann, Neil AU - Platzner, Marco AU - Teich, Jürgen ID - 10625 JF - {EURASIP} Journal on Embedded Systems TI - Dynamically Reconfigurable Architectures (editorial) VL - 2007 ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10643 TI - Distributed Simulation of mobile Robots using EyeSim ER - TY - JOUR AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 10646 IS - 4 JF - IET Computers Digital Techniques KW - reconfigurable architectures KW - resource allocation KW - device reconfiguration time KW - dynamic hardware reconfiguration KW - dynamically reconfigurable hardware KW - light-weight runtime system KW - merge server distribute load KW - periodic real-time tasks KW - runtime system overheads KW - schedulability analysis KW - scheduling technique KW - server-based execution KW - synthesis tool flow SN - 1751-8601 TI - Server-based execution of periodic tasks on dynamically reconfigurable hardware VL - 1 ER - TY - GEN AU - Defo, Bertrand ID - 10647 TI - A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization ER - TY - GEN AU - Döhre, Sven ID - 10648 TI - Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10689 T2 - Architecture of Computing Systems (ARCS) TI - Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution VL - 4415 ER - TY - GEN AU - Meiche, Robert ID - 10709 TI - VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen ER - TY - GEN AU - Reisch, Waldemar ID - 10728 TI - Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS ER - TY - GEN AU - Rethmeier, Eike ID - 10729 TI - Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem ER -