TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13642 T2 - Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian AU - Keller, Ariane AU - Plattner, Bernhard ID - 2223 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - GEN ED - Plaks, Toomas P. ED - Andrews, David ED - DeMara, Ronald ED - Lam, Herman ED - Lee, Jooheung ED - Plessl, Christian ED - Stitt, Greg ID - 2222 SN - 1-60132-140-6 TI - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) ER - TY - CONF AU - Beisel, Tobias AU - Niekamp, Manuel AU - Plessl, Christian ID - 2226 SN - 978-1-4244-6965-9 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco AU - Winkler, Michael ID - 10639 T2 - Proc. Technically Assisted Rehabilitation (TAR) TI - Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets ER - TY - GEN AU - Kostin, Alexander ID - 10702 TI - Evolvable Robot Controller ER - TY - JOUR AU - Lübbers, Enno AU - Platzner, Marco ID - 10703 IS - 1 JF - ACM Transactions on Embedded Computing Systems KW - Reconfigurable computing KW - multithreading KW - operating systems SN - 1539-9087 TI - ReconOS: Multithreaded Programming for Reconfigurable Computers VL - 9 ER - TY - GEN AU - Tofall, Martin ID - 10746 TI - Compiler for a Custom Instruction Set CPU ER - TY - GEN AU - Warkentin, Alexander ID - 10749 TI - Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units ER - TY - GEN AU - Wildenhain, Benedikt ID - 10753 TI - Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Miremadi, Seyed Ghassem AU - Ejlali, Alireza ID - 10777 T2 - Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on TI - Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors ER - TY - CONF AU - Happe, Markus AU - Lübbers, Enno AU - Platzner, Marco ID - 13632 T2 - Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC) TI - A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13634 T2 - Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS) TI - Towards Models for Many-Cores: The Case for the Reconfigurable Mesh ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13635 T2 - Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium TI - ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13636 T2 - Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) TI - Cooperative Multithreading in Dynamically Reconfigurable Systems ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13637 T2 - Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) TI - Program-driven Fine-grained Power Management for the Reconfigurable Mesh ER - TY - CONF AU - Happe, Markus AU - Lübbers, Enno AU - Platzner, Marco ID - 13638 SN - 9781424443758 T2 - Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT) TI - An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning ER - TY - CONF AU - Drzevitzky, Stephanie AU - Kastens, Uwe AU - Platzner, Marco ID - 13639 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules ER - TY - CONF AB - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2350 KW - IMORC KW - interconnect KW - performance SN - 978-1-4244-4450-2 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing ER - TY - CONF AB - In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 2262 KW - EvoCache KW - evolvable hardware KW - computer architecture T2 - Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) TI - EvoCaches: Application-specific Adaptation of Cache Mapping ER - TY - CONF AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2238 KW - IMORC KW - graphics SN - 978-0-7695-3917-1 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2261 KW - IMORC KW - NOC KW - KNN KW - accelerator SN - 1946-1488 T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure ER - TY - CONF AB - In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. AU - Grad, Mariusz AU - Plessl, Christian ID - 2263 SN - 1-60132-101-5 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX ER - TY - CONF AU - Beisel, Tobias AU - Lietsch, Stefan AU - Thielemans, Kris ID - 2358 T2 - IEEE Nuclear Science Symposium Conference Record (NSS) TI - A method for OSEM PET reconstruction on parallel architectures using STIR ER - TY - CONF AU - Platzner, Marco AU - Döhre, Sven AU - Happe, Markus AU - Kenter, Tobias AU - Lorenz, Ulf AU - Schumacher, Tobias AU - Send, Andre AU - Warkentin, Alexander ID - 2365 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - The GOmputer: Accelerating GO with FPGAs ER - TY - GEN AU - Boschmann, Alexander ID - 10628 TI - Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen ER - TY - GEN AU - Breitlauch, Daniel ID - 10641 TI - Selbstoptimierender Cache-Kontroller ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10644 TI - Verteilte Simulation von mobilen Robotern mit EyeSim ER - TY - CONF AU - Glette, Kyrre AU - Gruber, Thiemo AU - Kaufmann, Paul AU - Torresen, Jim AU - Sick, Bernhard AU - Platzner, Marco ID - 10653 T2 - IEEE Adaptive Hardware and Systems (AHS) TI - Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control ER - TY - CONF AU - Glette, Kyrre AU - Torresen, Jim AU - Kaufmann, Paul AU - Platzner, Marco ID - 10656 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - A Comparison of Evolvable Hardware Architectures for Classification Tasks VL - 5216 ER - TY - GEN AU - Happe, Markus ID - 10669 TI - Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern ER - TY - GEN AU - Torresen, Jim AU - Glette, Kyrre AU - Platzner, Marco AU - Kaufmann, Paul ID - 10690 TI - Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS) ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10691 T2 - Genetic and Evolutionary Computation (GECCO) TI - Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming ER - TY - GEN AU - Knieper, Tobias ID - 10696 TI - Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf ER - TY - CONF AU - Knieper, Tobias AU - Defo, Bertrand AU - Kaufmann, Paul AU - Platzner, Marco ID - 10698 T2 - Biologically Inspired Collaborative Computing (BICC) TI - On Robust Evolution of Digital Hardware VL - 268 ER - TY - GEN AU - Niklas, Jörg ID - 10718 TI - Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme ER - TY - GEN AU - Östermann, Marco ID - 10721 TI - Raytracing on a Custom Instruction Set CPU ER - TY - GEN AU - Westerheide, Nico ID - 10751 TI - Design and Evaluation of MicroBlaze Multi-core Architectures ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Tabkhi, Hamed AU - Miremadi, Seyed Ghassem AU - Ejlali, Alireza ID - 10778 T2 - 2008 International Conference on Microelectronics TI - A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13629 T2 - Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS) TI - Realizing Reconfigurable Mesh Algorithms on Softcore Arrays ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13630 T2 - Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Communication and Synchronization in Multithreaded Reconfigurable Computing Systems ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13631 SN - 9781424419609 T2 - Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL) TI - A portable abstraction layer for hardware threads ER - TY - CONF AU - Schumacher, Tobias AU - Meiche, Robert AU - Kaufmann, Paul AU - Lübbers, Enno AU - Plessl, Christian AU - Platzner, Marco ID - 2364 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Hardware Accelerator for k-th Nearest Neighbor Thinning ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2372 KW - IMORC KW - IP core KW - interconnect T2 - Many-core and Reconfigurable Supercomputing Conference (MRSC) TI - IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers ER - TY - CONF AB - In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits. AU - Kaufmann, Paul AU - Platzner, Marco ID - 6508 KW - integrated circuit design KW - hardware evolution KW - evolutionary hardware design KW - evolutionary optimizers KW - hash functions KW - preengineered circuits KW - Hardware KW - Circuits KW - Design optimization KW - Visualization KW - Genetic programming KW - Genetic mutations KW - Clustering algorithms KW - Biological cells KW - Field programmable gate arrays KW - Routing SN - 076952866X T2 - Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) TI - MOVES: A Modular Framework for Hardware Evolution ER - TY - GEN AU - Beisel, Tobias ID - 10623 TI - Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen ER - TY - JOUR AU - Bergmann, Neil AU - Platzner, Marco AU - Teich, Jürgen ID - 10625 JF - {EURASIP} Journal on Embedded Systems TI - Dynamically Reconfigurable Architectures (editorial) VL - 2007 ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10643 TI - Distributed Simulation of mobile Robots using EyeSim ER - TY - JOUR AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 10646 IS - 4 JF - IET Computers Digital Techniques KW - reconfigurable architectures KW - resource allocation KW - device reconfiguration time KW - dynamic hardware reconfiguration KW - dynamically reconfigurable hardware KW - light-weight runtime system KW - merge server distribute load KW - periodic real-time tasks KW - runtime system overheads KW - schedulability analysis KW - scheduling technique KW - server-based execution KW - synthesis tool flow SN - 1751-8601 TI - Server-based execution of periodic tasks on dynamically reconfigurable hardware VL - 1 ER - TY - GEN AU - Defo, Bertrand ID - 10647 TI - A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization ER - TY - GEN AU - Döhre, Sven ID - 10648 TI - Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10689 T2 - Architecture of Computing Systems (ARCS) TI - Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution VL - 4415 ER - TY - GEN AU - Meiche, Robert ID - 10709 TI - VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen ER - TY - GEN AU - Reisch, Waldemar ID - 10728 TI - Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS ER - TY - GEN AU - Rethmeier, Eike ID - 10729 TI - Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem ER - TY - CONF AU - Schumacher, Tobias AU - Lübbers, Enno AU - Kaufmann, Paul AU - Platzner, Marco ID - 10735 T2 - Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) TI - Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster VL - 15 ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13627 SN - 9781424410590 T2 - Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) TI - A Many-Core Implementation Based on the Reconfigurable Mesh Model ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13628 SN - 9781424410590 T2 - Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) TI - ReconOS: An RTOS Supporting Hard-and Software Threads ER - TY - CONF AB - This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. AU - Plessl, Christian AU - Platzner, Marco AU - Thiele, Lothar ID - 2401 KW - temporal partitioning KW - retiming KW - ILP T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - Optimal Temporal Partitioning based on Slowdown and Retiming ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10688 T2 - Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD) TI - Multi-objective Intrinsic Hardware Evolution ER - TY - GEN AU - Mühlenbernd, Roland ID - 10716 TI - FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks ER - TY - CONF AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 13624 T2 - Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) TI - Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13625 T2 - In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) TI - An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13626 T2 - Proceedings of the 13th Reconfigurable Architectures Workshop (RAW) TI - Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware ER - TY - CONF AB - This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. AU - Plessl, Christian AU - Platzner, Marco ID - 2411 KW - Zippy T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Zippy – A coarse-grained reconfigurable array with support for hardware virtualization ER - TY - JOUR AB - Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2412 IS - 2-3 JF - Microprocessors and Microsystems KW - FPGA KW - reconfigurable computing KW - co-simulation KW - Zippy TI - System-level performance evaluation of reconfigurable processors VL - 29 ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13621 SN - 3902463031 T2 - Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES) TI - Periodic real-time scheduling for FPGA computers ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13622 T2 - Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS) TI - Memory-demanding Periodic Real-time Applications on FPGA Computers ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13623 SN - 0780393627 T2 - Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL) TI - A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware ER - TY - CONF AB - In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. AU - Plessl, Christian AU - Platzner, Marco ID - 2415 KW - hardware virtualization T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Virtualization of Hardware – Introduction and Survey ER - TY - JOUR AU - Steiger, Christoph AU - Walder, Herbert AU - Platzner, Marco ID - 10742 IS - 11 JF - {IEEE} Transactions on Computers TI - Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks VL - 53 ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13618 SN - 0302-9743 T2 - Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) TI - A Runtime Environment for Reconfigurable Hardware Operating Systems ER - TY - CONF AU - Walder, Hebert AU - Nobs, Samuel AU - Platzner, Marco ID - 13619 T2 - Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems ER - TY - CONF AU - Dyer, Matthias AU - Platzner, Marco AU - Thiele, Lothar ID - 13620 SN - 0769522300 T2 - Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) TI - Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine ER - TY - CONF AB - This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. AU - Plessl, Christian AU - Platzner, Marco ID - 2418 KW - coprocessor KW - DIMM KW - memory bus KW - FPGA KW - high performance computing T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - TKDM – A Reconfigurable Co-processor in a PC's Memory Slot ER - TY - JOUR AB - Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM. AU - Plessl, Christian AU - Enzler, Rolf AU - Walder, Herbert AU - Beutel, Jan AU - Platzner, Marco AU - Thiele, Lothar AU - Tröster, Gerhard ID - 2419 IS - 5 JF - Personal and Ubiquitous Computing TI - The Case for Reconfigurable Hardware in Wearable Computing VL - 7 ER - TY - JOUR AB - This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. AU - Plessl, Christian AU - Platzner, Marco ID - 2420 IS - 2 JF - Journal of Supercomputing KW - reconfigurable computing KW - instance-specific acceleration KW - minimum covering SN - 0920-8542 TI - Instance-Specific Accelerators for Minimum Covering VL - 26 ER - TY - CONF AB - In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2421 KW - Zippy KW - multi-context KW - FPGA T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Virtualizing Hardware with Multi-Context Reconfigurable Arrays VL - 2778 ER - TY - CONF AB - Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2422 KW - Zippy KW - co-simulation SN - 1-932415-05-X T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Co-simulation of a Hybrid Multi-Context Architecture ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13612 SN - 0769518702 T2 - Proceedings Design, Automation and Test in Europe Conference (DATE) TI - Online scheduling for block-partitioned reconfigurable devices ER - TY - CONF AU - Walder, Herbert AU - Steiger, Christoph AU - Platzner, Marco ID - 13613 SN - 0769519261 T2 - Proceedings International Parallel and Distributed Processing Symposium TI - Fast online task placement on FPGAs: free space partitioning and 2D-hashing ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13614 T2 - Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations ER - TY - CONF AU - Steiger, Christoph AU - Walder, Herbert AU - Platzner, Marco ID - 13615 SN - 0302-9743 T2 - Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) TI - Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices ER - TY - CONF AU - Steiger, Christoph AU - Walder, Herbert AU - Platzner, Marco AU - Thiele, Lothar ID - 13617 SN - 0769520448 T2 - Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) TI - Online scheduling and placement of real-time tasks to partially reconfigurable devices ER - TY - CONF AB - Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM. AU - Plessl, Christian AU - Enzler, Rolf AU - Walder, Herbert AU - Beutel, Jan AU - Platzner, Marco AU - Thiele, Lothar ID - 2423 KW - wearable computing SN - 0-7695-1816-8 T2 - Proc. Int. Symp. on Wearable Computers (ISWC) TI - Reconfigurable Hardware in Wearable Computing Nodes ER - TY - CONF AB - Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. AU - Dyer, Matthias AU - Plessl, Christian AU - Platzner, Marco ID - 2424 KW - partial reconfiguration T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Partially Reconfigurable Cores for Xilinx Virtex VL - 2438 ER - TY - CONF AB - We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. AU - Plessl, Christian AU - Platzner, Marco ID - 2425 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - Custom Computing Machines for the Set Covering Problem ER - TY - JOUR AU - Eisenring, Michael AU - Platzner, Marco ID - 10651 IS - 2 JF - The Journal of Supercomputing TI - A Framework for Run-time Reconfigurable Systems VL - 21 ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13611 T2 - Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform ER - TY - CONF AB - In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. AU - Plessl, Christian AU - Platzner, Marco ID - 2428 KW - minimum covering KW - accelerator KW - funding-sundance T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Instance-Specific Accelerators for Minimum Covering ER - TY - CONF AB - In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core. AU - Enzler, Rolf AU - Platzner, Marco AU - Plessl, Christian AU - Thiele, Lothar AU - Tröster, Gerhard ID - 2432 KW - benchmark T2 - Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III TI - Reconfigurable Processors for Handhelds and Wearables: Application Analysis VL - 4525 ER - TY - JOUR AU - Mencer, Oskar AU - Platzner, Marco AU - Morf, Martin AU - J. Flynn, Michael ID - 10713 IS - 1 JF - {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems TI - Object-oriented domain specific compilers for programming FPGAs VL - 9 ER - TY - GEN AU - Enzler, Rolf AU - Platzner, Marco ID - 13463 TI - Dynamically Reconfigurable Processors ER - TY - JOUR AU - Platzner, Marco ID - 6507 IS - 4 JF - Computer SN - 0018-9162 TI - Reconfigurable accelerators for combinatorial problems VL - 33 ER - TY - JOUR AU - Eisenring, Michael AU - Platzner, Marco ID - 10606 JF - IEE Proceedings -- Computers & Digital Techniques TI - Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems VL - 147 ER -