TY - JOUR AB - Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 17358 IS - 9 JF - IEEE Transactions On Very Large Scale Integration Systems KW - Approximate circuit synthesis KW - approximate computing KW - error metrics KW - formal verification KW - proof-carrying hardware SN - 1063-8210 TI - Proof-carrying Approximate Circuits VL - 28 ER - TY - JOUR AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 17369 JF - International Journal of Hybrid intelligent Systems TI - Evolution of Application-Specific Cache Mappings ER - TY - GEN AB - On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies. In the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. In this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification. In our experimental results, we present the runtimes of our approach. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 20748 T2 - Fifth Workshop on Approximate Computing (AxC 2020) TI - Search Space Characterization for AxC Synthesis ER - TY - CONF AU - Lienen, Christian AU - Platzner, Marco AU - Rinner, Bernhard ID - 20750 T2 - Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT) TI - ReconROS: Flexible Hardware Acceleration for ROS2 Applications ER - TY - GEN AU - Thiele, Simon ID - 20820 TI - Implementing Machine Learning Functions as PYNQ FPGA Overlays ER - TY - GEN AU - Jaganath, Vivek ID - 20821 TI - Extension and Evaluation of Python-based High-Level Synthesis Tool Flows ER - TY - CONF AU - Hansmeier, Tim AU - Kaufmann, Paul AU - Platzner, Marco ID - 17063 SN - 978-1-4503-7127-8 T2 - GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - An Adaption Mechanism for the Error Threshold of XCSF ER - TY - JOUR AB - Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application. AU - Anwer, Jahanzeb AU - Meisner, Sebastian AU - Platzner, Marco ID - 17092 JF - International Journal of Reconfigurable Computing SN - 1687-7195 TI - Dynamic Reliability Management for FPGA-Based Systems ER - TY - JOUR AU - Bellman, K. AU - Dutt, N. AU - Esterle, L. AU - Herkersdorf, A. AU - Jantsch, A. AU - Landauer, C. AU - R. Lewis, P. AU - Platzner, Marco AU - TaheriNejad, N. AU - Tammemäe, K. ID - 15836 JF - ACM Transactions on Cyber-Physical Systems TI - Self-aware Cyber-Physical Systems VL - Accepted for Publication ER - TY - CONF AB - Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 16213 T2 - Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 TI - A Hybrid Synthesis Methodology for Approximate Circuits ER - TY - CONF AU - Hansmeier, Tim AU - Kaufmann, Paul AU - Platzner, Marco ID - 16363 SN - 978-1-4503-7127-8 T2 - GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold ER - TY - CONF AU - Lösch, Achim AU - Platzner, Marco ID - 20838 SN - 9781728174457 T2 - 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) TI - MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes ER - TY - GEN AB - Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware. This thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable computing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands. AU - Jentzsch, Felix P. ID - 21433 TI - Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture ER - TY - JOUR AB - Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Ghasemzadeh Mohammadi, Hassan AU - Awais, Muhammad AU - Platzner, Marco ID - 3585 JF - Microelectronics Reliability KW - Approximate Computing KW - Framework KW - Pareto Front KW - Accuracy SN - 0026-2714 TI - CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation VL - 99 ER - TY - GEN AB - State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing. AU - Witschen, Linus Matthias AU - Ghasemzadeh Mohammadi, Hassan AU - Artmann, Matthias AU - Platzner, Marco ID - 16853 KW - Approximate computing KW - parameter selection KW - search space exploration KW - verification KW - circuit synthesis T2 - Fourth Workshop on Approximate Computing (AxC 2019) TI - Jump Search: A Fast Technique for the Synthesis of Approximate Circuits ER - TY - CONF AB - State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution. In this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing. AU - Witschen, Linus Matthias AU - Ghasemzadeh Mohammadi, Hassan AU - Artmann, Matthias AU - Platzner, Marco ID - 10577 KW - Approximate computing KW - design automation KW - parameter selection KW - circuit synthesis SN - 9781450362528 T2 - Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19 TI - Jump Search: A Fast Technique for the Synthesis of Approximate Circuits ER - TY - JOUR AB - Advances in electromyographic (EMG) sensor technology and machine learning algorithms have led to an increased research effort into high density EMG-based pattern recognition methods for prosthesis control. With the goal set on an autonomous multi-movement prosthesis capable of performing training and classification of an amputee’s EMG signals, the focus of this paper lies in the acceleration of the embedded signal processing chain. We present two Xilinx Zynq-based architectures for accelerating two inherently different high density EMG-based control algorithms. The first hardware accelerated design achieves speed-ups of up to 4.8 over the software-only solution, allowing for a processing delay lower than the sample period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only version and operates at a still satisfactory low processing delay of up to 15 ms while providing a higher reliability and robustness against electrode shift and noisy channels. AU - Boschmann, Alexander AU - Agne, Andreas AU - Thombansen, Georg AU - Witschen, Linus Matthias AU - Kraus, Florian AU - Platzner, Marco ID - 11950 JF - Journal of Parallel and Distributed Computing KW - High density electromyography KW - FPGA acceleration KW - Medical signal processing KW - Pattern recognition KW - Prosthetics SN - 0743-7315 TI - Zynq-based acceleration of robust high density myoelectric signal processing VL - 123 ER - TY - JOUR AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Pantho, Md Jubaer Hossain AU - Andrews, David ID - 12967 IS - 11 JF - Journal of Signal Processing Systems SN - 1939-8018 TI - An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology VL - 91 ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 15422 T2 - World Congress on Nature and Biologically Inspired Computing (NaBIC) TI - Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor ER - TY - GEN AU - Kumar Jeyakumar, Shankar ID - 15883 TI - Incremental learning with Support Vector Machine on embedded platforms ER - TY - GEN AB - Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis. AU - Keerthipati, Monica ID - 15920 TI - A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking ER - TY - GEN AU - Sabu, Nithin S. ID - 14831 TI - FPGA Acceleration of String Search Techniques in Huge Data Sets ER - TY - GEN AU - Mehta, Jinay ID - 15946 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip ER - TY - GEN AU - Hansmeier, Tim ID - 14546 TI - Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers ER - TY - CONF AU - Guettatfi, Zakarya AU - Platzner, Marco AU - Kermia, Omar AU - Khouas, Abdelhakim ID - 31067 T2 - 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) TI - An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware ER - TY - CONF AB - Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers. AU - Ahmed, Qazi Arbab AU - Wiersema, Tobias AU - Platzner, Marco ED - Hochberger, Christian ED - Nelson, Brent ED - Koch, Andreas ED - Woods, Roger ED - Diniz, Pedro ID - 9913 SN - 978-3-030-17227-5 T2 - Applied Reconfigurable Computing TI - Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan VL - 11444 ER - TY - GEN AU - Lienen, Christian ID - 15874 TI - Implementing a Real-time System on a Platform FPGA operated with ReconOS ER - TY - JOUR AU - Platzner, Marco AU - Plessl, Christian ID - 12871 JF - Informatik Spektrum SN - 0170-6012 TI - FPGAs im Rechenzentrum ER - TY - GEN AU - Mehta, Jinay D ID - 52478 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip ER - TY - CONF AB - Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node. AU - Lösch, Achim AU - Wiens, Alex AU - Platzner, Marco ID - 3362 SN - 0302-9743 T2 - Proceedings of the International Conference on Architecture of Computing Systems (ARCS) TI - Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes VL - 10793 ER - TY - GEN AU - Schnuer, Jan-Philip ID - 3365 TI - Static Scheduling Algorithms for Heterogeneous Compute Nodes ER - TY - GEN AU - Croce, Marcel ID - 3366 TI - Evaluation of OpenCL-based Compilation for FPGAs ER - TY - CONF AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Andrews, David ID - 3373 SN - 0302-9743 T2 - ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications TI - An FPGA/HMC-Based Accelerator for Resolution Proof Checking VL - 10824 ER - TY - GEN AB - Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Ghasemzadeh Mohammadi, Hassan AU - Awais, Muhammad AU - Platzner, Marco ID - 3586 KW - Approximate Computing KW - Framework KW - Pareto Front KW - Accuracy T2 - Third Workshop on Approximate Computing (AxC 2018) TI - CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation ER - TY - THES AB - Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches. AU - Ho, Nam ID - 3720 TI - FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization ER - TY - GEN AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 1165 T2 - 4th Workshop On Approximate Computing (WAPCO 2018) TI - Making the Case for Proof-carrying Approximate Circuits ER - TY - CONF AU - Lösch, Achim AU - Platzner, Marco ID - 5547 SN - 9781538674796 T2 - 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes ER - TY - CONF AB - Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 10598 KW - Approximate computing KW - High-level synthesis KW - Accuracy KW - Monte-Carlo tree search KW - Circuit simulation T2 - 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) TI - An MCTS-based Framework for Synthesis of Approximate Circuits ER - TY - GEN AU - Clausing, Lennart ID - 10782 TI - Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data ER - TY - GEN AU - Jentzsch, Felix Paul ID - 1097 KW - Approximate Computing KW - Proof-Carrying Hardware KW - Formal Verification TI - Enforcing IP Core Connection Properties with Verifiable Security Monitors ER - TY - JOUR AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Li, Zhiwu AU - Alnowibet, Khalid AU - Platzner, Marco ID - 12965 JF - IEEE Access SN - 2169-3536 TI - R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints ER - TY - GEN AU - Hansmeier, Tim ID - 3580 TI - An FPGA Accelerator for Checking Resolution Proofs ER - TY - GEN AU - Witschen, Linus Matthias ID - 1157 TI - A Framework for the Synthesis of Approximate Circuits ER - TY - GEN AU - Knorr, Christoph ID - 74 TI - OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten ER - TY - JOUR AB - This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network. AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 9919 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) KW - Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies VL - 94 ER - TY - CONF AB - Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules. AU - Lösch, Achim AU - Platzner, Marco ID - 65 T2 - Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements ER - TY - JOUR AB - Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits. AU - Isenberg, Tobias AU - Platzner, Marco AU - Wehrheim, Heike AU - Wiersema, Tobias ID - 68 IS - 4 JF - ACM Transactions on Design Automation of Electronic Systems TI - Proof-Carrying Hardware via Inductive Invariants ER - TY - JOUR AU - H.W. Leong, Philip AU - Amano, Hideharu AU - Anderson, Jason AU - Bertels, Koen AU - M.P. Cardoso, Jo\~{a}o AU - Diessel, Oliver AU - Gogniat, Guy AU - Hutton, Mike AU - Lee, JunKyu AU - Luk, Wayne AU - Lysaght, Patrick AU - Platzner, Marco AU - K. Prasanna, Viktor AU - Rissa, Tero AU - Silvano, Cristina AU - So, Hayden AU - Wang, Yu ID - 10600 JF - ACM Transactions on Reconfigurable Technology and Systems TI - The First 25 Years of the FPL Conference – Significant Papers ER - TY - JOUR AU - F. DeMara, Ronald AU - Platzner, Marco AU - Ottavi, Marco ID - 10601 JF - IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing TI - Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial) ER - TY - JOUR AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10611 JF - Microprocessors and Microsystems TI - Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus ER - TY - GEN AU - Kaltschmidt, Christian ID - 10613 TI - An AR-based Training and Assessment System for Myoelectrical Prosthetic Control ER - TY - CONF AU - Boschmann, Alexander AU - Thombansen, Georg AU - Witschen, Linus Matthias AU - Wiens, Alex AU - Platzner, Marco ID - 10630 T2 - Design, Automation and Test in Europe (DATE) TI - A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller ER - TY - GEN AU - Riaz, Umair ID - 10666 TI - Acceleration of Industrial Analytics Functions on a Platform FPGA ER - TY - CONF AU - Ho, Nam AU - Ashraf, Ishraq Ibne AU - Kaufmann, Paul AU - Platzner, Marco ID - 10672 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10676 KW - Linux KW - cache storage KW - microprocessor chips KW - multiprocessing systems KW - LEON3-Linux based multicore processor KW - MiBench suite KW - block sizes KW - cache adaptation KW - evolvable caches KW - memory-to-cache-index mapping function KW - processor caches KW - reconfigurable cache mapping optimization KW - reconfigurable hardware technology KW - replacement strategies KW - standard Linux OS KW - time a complete hardware implementation KW - Hardware KW - Indexes KW - Linux KW - Measurement KW - Multicore processing KW - Optimization KW - Training T2 - 2017 International Conference on Field Programmable Technology (ICFPT) TI - Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10692 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies ER - TY - GEN AU - Dietrich, Andreas ID - 10708 TI - Reconfigurable Cryptographic Services ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10740 JF - The Journal of Engineering TI - Fast Network Restoration by Partitioning of Parallel Black Start Zones ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10759 TI - Applications of Evolutionary Computation - 20th European Conference, EvoApplications ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10760 T2 - KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI TI - Parametrizing Cartesian Genetic Programming: An Empirical Study ER - TY - CONF AU - Kaufmann, Paul AU - Ho, Nam AU - Platzner, Marco ID - 10761 T2 - Adaptive Hardware and Systems (AHS) TI - Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10762 T2 - Genetic and Evolutionary Computation (GECCO), Compendium TI - An Empirical Study on the Parametrization of Cartesian Genetic Programming ER - TY - CONF AU - Guettatfi, Zakarya AU - Hübner, Philipp AU - Platzner, Marco AU - Rinner, Bernhard ID - 10780 KW - embedded systems KW - image sensors KW - power aware computing KW - wireless sensor networks KW - Zynq-based VSN node prototype KW - computational self-awareness KW - design approach KW - platform levels KW - power consumption KW - visual sensor networks KW - visual sensor nodes KW - Cameras KW - Hardware KW - Middleware KW - Multicore processing KW - Operating systems KW - Runtime KW - Reconfigurable platforms KW - distributed embedded systems KW - performance-resource trade-off KW - self-awareness KW - visual sensor nodes T2 - 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Computational self-awareness as design approach for visual sensor nodes ER - TY - CONF AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Platzner, Marco ID - 14893 SN - 1865-0929 T2 - Communications in Computer and Information Science TI - I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems ER - TY - JOUR AB - Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved. AU - Wiersema, Tobias AU - Bockhorn, Arne AU - Platzner, Marco ID - 222 JF - Computers & Electrical Engineering TI - An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 5812 SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - GEN AU - Cedric Mertens, Jan ID - 10612 TI - Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion ER - TY - GEN AU - Nassery, Abdul Sami ID - 10616 TI - Implementation of Bilinear Pairings on Reconfigurable Hardware ER - TY - GEN AU - Amin, Omair ID - 10617 TI - Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10622 T2 - Euromicro Conference on Digital System Design (DSD) TI - Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs ER - TY - CONF AU - Boschmann, Alexander AU - Dosen, Strahinja AU - Werner, Andreas AU - Raies, Ali AU - Farina, Dario ID - 10631 T2 - Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI) TI - A novel immersive augmented reality system for prosthesis training and assessment ER - TY - JOUR AU - Graf, Tobias AU - Platzner, Marco ID - 10661 JF - Journal Theoretical Computer Science TI - Adaptive playouts for online learning of policies during Monte Carlo Tree Search VL - 644 ER - TY - GEN AU - Horstmann, Jens ID - 10695 TI - Beschleunigte Simulation elektrischer Stromnetze mit GPUs ER - TY - JOUR AU - Ma, Chenjie AU - Kaufmann, Paul AU - Töbermann, J.-Christian AU - Braun, Martin ID - 10705 IS - (part 2) JF - Renewable Energy TI - Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control VL - 87 ER - TY - GEN AU - Makeswaran, Vignesh ID - 10706 TI - Operating System Support for Reconfigurable Cache ER - TY - GEN AU - Ibne Ashraf, Ishraq ID - 10707 TI - Private/Shared Data Classification and Implementation for a Multi-Softcore Platform ER - TY - CONF AU - Meisner, Sebastian AU - Platzner, Marco ID - 10712 T2 - Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on TI - Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level ER - TY - GEN AU - Schmidt, Marco ID - 10755 TI - Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10758 TI - Applications of Evolutionary Computation - 19th European Conference, EvoApplications VL - 9597 ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10766 T2 - Proceedings of the 30th European Simulation and Modelling Conference (ESM) TI - RCo-Design: New Visual Environment for Reconfigurable Embedded Systems ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10768 T2 - Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) TI - New Co-design Methodology for Real-time Embedded Systems ER - TY - JOUR AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10769 IS - 99 JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems TI - Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation VL - PP ER - TY - GEN AU - Hermansen, Sven ID - 10781 TI - Custom Memory Controller for ReconOS ER - TY - BOOK AB - Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering. ED - Lewis, Peter R. ED - Platzner, Marco ED - Rinner, Bernhard ED - Tørresen, Jim ED - Yao, Xin ID - 12972 SN - 1619-7127 TI - Self-aware Computing Systems: An Engineering Approach ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus Matthias AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 15873 KW - Electromyography KW - Feature extraction KW - Delays KW - Hardware Pattern recognition KW - Prosthetics KW - High definition video SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13151 T2 - Computer and Games TI - Using Deep Convolutional Neural Networks in Monte Carlo Tree Search ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13152 T2 - IEEE Computational Intelligence and Games TI - Monte-Carlo Simulation Balancing Revisited ER - TY - CONF AB - Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module. AU - Wiersema, Tobias AU - Platzner, Marco ID - 132 T2 - Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) TI - Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware ER - TY - CHAP AB - In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. AU - Agne, Andreas AU - Platzner, Marco AU - Plessl, Christian AU - Happe, Markus AU - Lübbers, Enno ED - Koch, Dirk ED - Hannig, Frank ED - Ziener, Daniel ID - 29 SN - 978-3-319-26406-6 T2 - FPGAs for Software Programmers TI - ReconOS ER - TY - CHAP AB - Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 156 T2 - Self-aware Computing Systems TI - Self-aware Compute Nodes ER - TY - CONF AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. AU - Lösch, Achim AU - Beisel, Tobias AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 168 T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center ER - TY - CONF AB - Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level. AU - Wiersema, Tobias AU - Wu, Sen AU - Platzner, Marco ID - 269 T2 - Proceedings of the International Symposium in Reconfigurable Computing (ARC) TI - On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach ER - TY - GEN AU - Knorr, Christoph ID - 3364 TI - Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten ER - TY - JOUR AU - Torresen, Jim AU - Plessl, Christian AU - Yao, Xin ID - 1772 IS - 7 JF - IEEE Computer KW - self-awareness KW - self-expression TI - Self-Aware and Self-Expressive Systems – Guest Editor's Introduction VL - 48 ER - TY - GEN AU - Ahmed, Abdullah Fathi ID - 10615 TI - Self-Optimizing Organic Cache ER - TY - THES AB - The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies. AU - Beisel, Tobias ID - 10624 SN - 978-3-8325-4155-2 TI - Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing ER - TY - GEN AU - Hangmann, Hendrik ID - 10668 TI - Evolution of Heat Flow Prediction Models for FPGA Devices ER - TY - GEN AU - Haupt, Christian ID - 10671 TI - Computer Vision basierte Klassifikation von HD EMG Signalen ER - TY - CONF AU - Ho, Nam AU - Ahmed, Abdullah Fathi AU - Kaufmann, Paul AU - Platzner, Marco ID - 10673 KW - cache storage KW - field programmable gate arrays KW - multiprocessing systems KW - parallel architectures KW - reconfigurable architectures KW - FPGA KW - dynamic reconfiguration KW - evolvable cache mapping KW - many-core architecture KW - memory-to-cache address mapping function KW - microarchitectural optimization KW - multicore architecture KW - nature-inspired optimization KW - parallelization degrees KW - processor KW - reconfigurable cache mapping KW - reconfigurable computing KW - Field programmable gate arrays KW - Software KW - Tuning T2 - Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) TI - Microarchitectural optimization by means of reconfigurable and evolvable cache mappings ER - TY - CONF AU - Kaufmann, Paul AU - Shen, Cong ID - 10693 T2 - Genetic and Evolutionary Computation (GECCO) TI - Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing ER -