TY - GEN AU - Schnuer, Jan-Philip ID - 3365 TI - Static Scheduling Algorithms for Heterogeneous Compute Nodes ER - TY - GEN AU - Croce, Marcel ID - 3366 TI - Evaluation of OpenCL-based Compilation for FPGAs ER - TY - CONF AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Andrews, David ID - 3373 SN - 0302-9743 T2 - ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications TI - An FPGA/HMC-Based Accelerator for Resolution Proof Checking VL - 10824 ER - TY - GEN AB - Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Ghasemzadeh Mohammadi, Hassan AU - Awais, Muhammad AU - Platzner, Marco ID - 3586 KW - Approximate Computing KW - Framework KW - Pareto Front KW - Accuracy T2 - Third Workshop on Approximate Computing (AxC 2018) TI - CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation ER - TY - THES AB - Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches. AU - Ho, Nam ID - 3720 TI - FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization ER - TY - GEN AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 1165 T2 - 4th Workshop On Approximate Computing (WAPCO 2018) TI - Making the Case for Proof-carrying Approximate Circuits ER - TY - CONF AU - Lösch, Achim AU - Platzner, Marco ID - 5547 SN - 9781538674796 T2 - 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes ER - TY - CONF AB - Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 10598 KW - Approximate computing KW - High-level synthesis KW - Accuracy KW - Monte-Carlo tree search KW - Circuit simulation T2 - 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) TI - An MCTS-based Framework for Synthesis of Approximate Circuits ER - TY - GEN AU - Clausing, Lennart ID - 10782 TI - Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data ER - TY - GEN AU - Jentzsch, Felix Paul ID - 1097 KW - Approximate Computing KW - Proof-Carrying Hardware KW - Formal Verification TI - Enforcing IP Core Connection Properties with Verifiable Security Monitors ER - TY - JOUR AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Li, Zhiwu AU - Alnowibet, Khalid AU - Platzner, Marco ID - 12965 JF - IEEE Access SN - 2169-3536 TI - R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints ER - TY - GEN AU - Hansmeier, Tim ID - 3580 TI - An FPGA Accelerator for Checking Resolution Proofs ER - TY - GEN AU - Witschen, Linus Matthias ID - 1157 TI - A Framework for the Synthesis of Approximate Circuits ER - TY - GEN AU - Knorr, Christoph ID - 74 TI - OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten ER - TY - JOUR AB - This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network. AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 9919 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) KW - Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies VL - 94 ER - TY - CONF AB - Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules. AU - Lösch, Achim AU - Platzner, Marco ID - 65 T2 - Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements ER - TY - JOUR AB - Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits. AU - Isenberg, Tobias AU - Platzner, Marco AU - Wehrheim, Heike AU - Wiersema, Tobias ID - 68 IS - 4 JF - ACM Transactions on Design Automation of Electronic Systems TI - Proof-Carrying Hardware via Inductive Invariants ER - TY - JOUR AU - H.W. Leong, Philip AU - Amano, Hideharu AU - Anderson, Jason AU - Bertels, Koen AU - M.P. Cardoso, Jo\~{a}o AU - Diessel, Oliver AU - Gogniat, Guy AU - Hutton, Mike AU - Lee, JunKyu AU - Luk, Wayne AU - Lysaght, Patrick AU - Platzner, Marco AU - K. Prasanna, Viktor AU - Rissa, Tero AU - Silvano, Cristina AU - So, Hayden AU - Wang, Yu ID - 10600 JF - ACM Transactions on Reconfigurable Technology and Systems TI - The First 25 Years of the FPL Conference – Significant Papers ER - TY - JOUR AU - F. DeMara, Ronald AU - Platzner, Marco AU - Ottavi, Marco ID - 10601 JF - IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing TI - Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial) ER - TY - JOUR AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10611 JF - Microprocessors and Microsystems TI - Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus ER - TY - GEN AU - Kaltschmidt, Christian ID - 10613 TI - An AR-based Training and Assessment System for Myoelectrical Prosthetic Control ER - TY - CONF AU - Boschmann, Alexander AU - Thombansen, Georg AU - Witschen, Linus Matthias AU - Wiens, Alex AU - Platzner, Marco ID - 10630 T2 - Design, Automation and Test in Europe (DATE) TI - A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller ER - TY - GEN AU - Riaz, Umair ID - 10666 TI - Acceleration of Industrial Analytics Functions on a Platform FPGA ER - TY - CONF AU - Ho, Nam AU - Ashraf, Ishraq Ibne AU - Kaufmann, Paul AU - Platzner, Marco ID - 10672 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10676 KW - Linux KW - cache storage KW - microprocessor chips KW - multiprocessing systems KW - LEON3-Linux based multicore processor KW - MiBench suite KW - block sizes KW - cache adaptation KW - evolvable caches KW - memory-to-cache-index mapping function KW - processor caches KW - reconfigurable cache mapping optimization KW - reconfigurable hardware technology KW - replacement strategies KW - standard Linux OS KW - time a complete hardware implementation KW - Hardware KW - Indexes KW - Linux KW - Measurement KW - Multicore processing KW - Optimization KW - Training T2 - 2017 International Conference on Field Programmable Technology (ICFPT) TI - Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10692 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies ER - TY - GEN AU - Dietrich, Andreas ID - 10708 TI - Reconfigurable Cryptographic Services ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10740 JF - The Journal of Engineering TI - Fast Network Restoration by Partitioning of Parallel Black Start Zones ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10759 TI - Applications of Evolutionary Computation - 20th European Conference, EvoApplications ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10760 T2 - KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI TI - Parametrizing Cartesian Genetic Programming: An Empirical Study ER - TY - CONF AU - Kaufmann, Paul AU - Ho, Nam AU - Platzner, Marco ID - 10761 T2 - Adaptive Hardware and Systems (AHS) TI - Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10762 T2 - Genetic and Evolutionary Computation (GECCO), Compendium TI - An Empirical Study on the Parametrization of Cartesian Genetic Programming ER - TY - CONF AU - Guettatfi, Zakarya AU - Hübner, Philipp AU - Platzner, Marco AU - Rinner, Bernhard ID - 10780 KW - embedded systems KW - image sensors KW - power aware computing KW - wireless sensor networks KW - Zynq-based VSN node prototype KW - computational self-awareness KW - design approach KW - platform levels KW - power consumption KW - visual sensor networks KW - visual sensor nodes KW - Cameras KW - Hardware KW - Middleware KW - Multicore processing KW - Operating systems KW - Runtime KW - Reconfigurable platforms KW - distributed embedded systems KW - performance-resource trade-off KW - self-awareness KW - visual sensor nodes T2 - 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Computational self-awareness as design approach for visual sensor nodes ER - TY - CONF AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Platzner, Marco ID - 14893 SN - 1865-0929 T2 - Communications in Computer and Information Science TI - I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems ER - TY - JOUR AB - Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved. AU - Wiersema, Tobias AU - Bockhorn, Arne AU - Platzner, Marco ID - 222 JF - Computers & Electrical Engineering TI - An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 5812 SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - GEN AU - Cedric Mertens, Jan ID - 10612 TI - Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion ER - TY - GEN AU - Nassery, Abdul Sami ID - 10616 TI - Implementation of Bilinear Pairings on Reconfigurable Hardware ER - TY - GEN AU - Amin, Omair ID - 10617 TI - Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10622 T2 - Euromicro Conference on Digital System Design (DSD) TI - Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs ER - TY - CONF AU - Boschmann, Alexander AU - Dosen, Strahinja AU - Werner, Andreas AU - Raies, Ali AU - Farina, Dario ID - 10631 T2 - Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI) TI - A novel immersive augmented reality system for prosthesis training and assessment ER - TY - JOUR AU - Graf, Tobias AU - Platzner, Marco ID - 10661 JF - Journal Theoretical Computer Science TI - Adaptive playouts for online learning of policies during Monte Carlo Tree Search VL - 644 ER - TY - GEN AU - Horstmann, Jens ID - 10695 TI - Beschleunigte Simulation elektrischer Stromnetze mit GPUs ER - TY - JOUR AU - Ma, Chenjie AU - Kaufmann, Paul AU - Töbermann, J.-Christian AU - Braun, Martin ID - 10705 IS - (part 2) JF - Renewable Energy TI - Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control VL - 87 ER - TY - GEN AU - Makeswaran, Vignesh ID - 10706 TI - Operating System Support for Reconfigurable Cache ER - TY - GEN AU - Ibne Ashraf, Ishraq ID - 10707 TI - Private/Shared Data Classification and Implementation for a Multi-Softcore Platform ER - TY - CONF AU - Meisner, Sebastian AU - Platzner, Marco ID - 10712 T2 - Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on TI - Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level ER - TY - GEN AU - Schmidt, Marco ID - 10755 TI - Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10758 TI - Applications of Evolutionary Computation - 19th European Conference, EvoApplications VL - 9597 ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10766 T2 - Proceedings of the 30th European Simulation and Modelling Conference (ESM) TI - RCo-Design: New Visual Environment for Reconfigurable Embedded Systems ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10768 T2 - Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) TI - New Co-design Methodology for Real-time Embedded Systems ER - TY - JOUR AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10769 IS - 99 JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems TI - Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation VL - PP ER - TY - GEN AU - Hermansen, Sven ID - 10781 TI - Custom Memory Controller for ReconOS ER - TY - BOOK AB - Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering. ED - Lewis, Peter R. ED - Platzner, Marco ED - Rinner, Bernhard ED - Tørresen, Jim ED - Yao, Xin ID - 12972 SN - 1619-7127 TI - Self-aware Computing Systems: An Engineering Approach ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus Matthias AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 15873 KW - Electromyography KW - Feature extraction KW - Delays KW - Hardware Pattern recognition KW - Prosthetics KW - High definition video SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13151 T2 - Computer and Games TI - Using Deep Convolutional Neural Networks in Monte Carlo Tree Search ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13152 T2 - IEEE Computational Intelligence and Games TI - Monte-Carlo Simulation Balancing Revisited ER - TY - CONF AB - Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module. AU - Wiersema, Tobias AU - Platzner, Marco ID - 132 T2 - Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) TI - Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware ER - TY - CHAP AB - In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. AU - Agne, Andreas AU - Platzner, Marco AU - Plessl, Christian AU - Happe, Markus AU - Lübbers, Enno ED - Koch, Dirk ED - Hannig, Frank ED - Ziener, Daniel ID - 29 SN - 978-3-319-26406-6 T2 - FPGAs for Software Programmers TI - ReconOS ER - TY - CHAP AB - Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 156 T2 - Self-aware Computing Systems TI - Self-aware Compute Nodes ER - TY - CONF AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. AU - Lösch, Achim AU - Beisel, Tobias AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 168 T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center ER - TY - CONF AB - Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level. AU - Wiersema, Tobias AU - Wu, Sen AU - Platzner, Marco ID - 269 T2 - Proceedings of the International Symposium in Reconfigurable Computing (ARC) TI - On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach ER - TY - GEN AU - Knorr, Christoph ID - 3364 TI - Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten ER - TY - JOUR AU - Torresen, Jim AU - Plessl, Christian AU - Yao, Xin ID - 1772 IS - 7 JF - IEEE Computer KW - self-awareness KW - self-expression TI - Self-Aware and Self-Expressive Systems – Guest Editor's Introduction VL - 48 ER - TY - GEN AU - Ahmed, Abdullah Fathi ID - 10615 TI - Self-Optimizing Organic Cache ER - TY - THES AB - The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies. AU - Beisel, Tobias ID - 10624 SN - 978-3-8325-4155-2 TI - Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing ER - TY - GEN AU - Hangmann, Hendrik ID - 10668 TI - Evolution of Heat Flow Prediction Models for FPGA Devices ER - TY - GEN AU - Haupt, Christian ID - 10671 TI - Computer Vision basierte Klassifikation von HD EMG Signalen ER - TY - CONF AU - Ho, Nam AU - Ahmed, Abdullah Fathi AU - Kaufmann, Paul AU - Platzner, Marco ID - 10673 KW - cache storage KW - field programmable gate arrays KW - multiprocessing systems KW - parallel architectures KW - reconfigurable architectures KW - FPGA KW - dynamic reconfiguration KW - evolvable cache mapping KW - many-core architecture KW - memory-to-cache address mapping function KW - microarchitectural optimization KW - multicore architecture KW - nature-inspired optimization KW - parallelization degrees KW - processor KW - reconfigurable cache mapping KW - reconfigurable computing KW - Field programmable gate arrays KW - Software KW - Tuning T2 - Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) TI - Microarchitectural optimization by means of reconfigurable and evolvable cache mappings ER - TY - CONF AU - Kaufmann, Paul AU - Shen, Cong ID - 10693 T2 - Genetic and Evolutionary Computation (GECCO) TI - Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing ER - TY - CONF AU - Meisner, Sebastian AU - Platzner, Marco ID - 10711 T2 - Field Programmable Technology (FPT), 2015 International Conference on TI - Comparison of thread signatures for error detection in hybrid multi-cores ER - TY - GEN AU - Meißner, Roland ID - 10714 TI - Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs ER - TY - GEN AU - Posewsky, Thorbjörn ID - 10726 TI - Acceleration of Artificial Neural Networks on a Zynq Platform ER - TY - BOOK AU - M. Mora, Antonio AU - Squillero, Giovanni AU - Agapitos, Alexandros AU - Burelli, Paolo AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10757 TI - Applications of Evolutionary Computation - 18th European Conference, EvoApplications VL - 9028 ER - TY - CONF AU - H.W. Leong, Philip AU - Amano, Hideharu AU - Anderson, Jason AU - Bertels, Koen AU - M.P. Cardoso, Jo\~ao AU - Diessel, Oliver AU - Gogniat, Guy AU - Hutton, Mike AU - Lee, JunKyu AU - Luk, Wayne AU - Lysaght, Patrick AU - Platzner, Marco AU - K. Prasanna, Viktor AU - Rissa, Tero AU - Silvano, Cristina AU - So, Hayden AU - Wang, Yu ID - 10765 T2 - Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) TI - Significant papers from the first 25 years of the FPL conference ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10767 T2 - Proceedings of the 29th European Simulation and Modelling Conference (ESM) TI - New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software ER - TY - JOUR AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10770 IS - 6 JF - IEEE Transactions on Nanotechnology TI - From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires VL - 14 ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Zhang, Jian AU - De Micheli, Giovanni AU - Sanchez, Eduardo AU - Reorda, Matteo Sonza ID - 10771 T2 - 2015 IEEE Computer Society Annual Symposium on VLSI TI - On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10772 T2 - Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition TI - Fault modeling in controllable polarity silicon nanowire circuits ER - TY - CONF AU - Guettatfi, Zakarya AU - Kermia, Omar AU - Khouas, Abdelhakim ID - 10779 KW - embedded systems KW - field programmable gate arrays KW - operating systems (computers) KW - scheduling KW - μC/OS-II KW - FPGAs KW - OS foundation KW - SafeRTOS KW - Xenomai KW - chip utilization ration KW - complex time constraints KW - embedded systems KW - hard real-time hardware task allocation KW - hard real-time hardware task scheduling KW - hardware-software real-time operating systems KW - partially reconfigurable field-programmable gate arrays KW - resource constraints KW - safety-critical RTOS KW - Field programmable gate arrays KW - Hardware KW - Job shop scheduling KW - Real-time systems KW - Shape KW - Software SN - 1946-147X T2 - 25th International Conference on Field Programmable Logic and Applications (FPL) TI - Over effective hard real-time hardware tasks scheduling and allocation ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13153 T2 - Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers TI - Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning ER - TY - JOUR AB - FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 296 JF - International Journal of Reconfigurable Computing (IJRC) TI - Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study VL - 2015 ER - TY - CONF AB - This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. AU - Damschen, Marvin AU - Plessl, Christian ID - 303 T2 - Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) TI - Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores ER - TY - CONF AU - Schumacher, Jörn AU - T. Anderson, J. AU - Borga, A. AU - Boterenbrood, H. AU - Chen, H. AU - Chen, K. AU - Drake, G. AU - Francis, D. AU - Gorini, B. AU - Lanni, F. AU - Lehmann-Miotto, Giovanna AU - Levinson, L. AU - Narevicius, J. AU - Plessl, Christian AU - Roich, A. AU - Ryu, S. AU - P. Schreuder, F. AU - Vandelli, Wainer AU - Vermeulen, J. AU - Zhang, J. ID - 1773 T2 - Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) TI - Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm ER - TY - JOUR AU - Plessl, Christian AU - Platzner, Marco AU - Schreier, Peter J. ID - 1768 IS - 5 JF - Informatik Spektrum KW - approximate computing KW - survey TI - Aktuelles Schlagwort: Approximate Computing ER - TY - CONF AB - In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. AU - Damschen, Marvin AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 238 T2 - Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) TI - Transparent offloading of computational hotspots from binary code to Xeon Phi ER - TY - CONF AB - Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead. AU - Meisner, Sebastian AU - Platzner, Marco ED - Goehringer, Diana ED - Santambrogio, MarcoDomenico ED - Cardoso, JoãoM.P. ED - Bertels, Koen ID - 347 T2 - Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC) TI - Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection ER - TY - CONF AU - Graf, Tobias AU - Schaefers, Lars AU - Platzner, Marco ID - 1782 IS - 8427 T2 - Proc. Conf. on Computers and Games (CG) TI - On Semeai Detection in Monte-Carlo Go ER - TY - CONF AB - Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric. AU - Wiersema, Tobias AU - Drzevitzky, Stephanie AU - Platzner, Marco ID - 399 T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring ER - TY - CONF AB - Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques. AU - Jakobs, Marie-Christine AU - Platzner, Marco AU - Wiersema, Tobias AU - Wehrheim, Heike ED - Albert, Elvira ED - Sekerinski, Emil ID - 408 T2 - Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) TI - Integrating Software and Hardware Verification ER - TY - CONF AB - Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA. AU - Wiersema, Tobias AU - Bockhorn, Arne AU - Platzner, Marco ID - 433 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA ER - TY - JOUR AU - Schaefers, Lars AU - Platzner, Marco ID - 10602 IS - 3 JF - IEEE Transactions on Computational Intelligence and AI in Games TI - A Novel Technique and its Application to Computer Go VL - 6 ER - TY - JOUR AU - Giefers, Heiner AU - Platzner, Marco ID - 10603 IS - 12 JF - IEEE Transactions on Computers TI - An FPGA-based Reconfigurable Mesh Many-Core VL - 63 ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco AU - Meisner, Sebastian ID - 10621 T2 - Reconfigurable Architectures Workshop (RAW) TI - FPGA Redundancy Configurations: An Automated Design Space Exploration ER - TY - GEN AU - Bockhorn, Arne ID - 10627 TI - Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10632 T2 - Proc. MyoElectric Controls Symposium (MEC) TI - A computer vision-based approach to high density EMG pattern recognition using structural similarity ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10633 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity ER - TY - GEN AU - Brand, Marcel ID - 10640 TI - A Generalized Loop Accelerator Implemented as a Coarse-Grained Array ER - TY - GEN AU - Damschen, Marvin ID - 10645 TI - Easy-to-use-on-the-fly binary program acceleration on many-cores ER - TY - CONF AU - Glette, Kyrre AU - Kaufmann, Paul ID - 10654 T2 - IEEE Congress on Evolutionary Computation (CEC) TI - Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System ER -