TY - CONF AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. AU - Lösch, Achim AU - Beisel, Tobias AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 168 T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center ER - TY - CONF AB - Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level. AU - Wiersema, Tobias AU - Wu, Sen AU - Platzner, Marco ID - 269 T2 - Proceedings of the International Symposium in Reconfigurable Computing (ARC) TI - On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach ER - TY - GEN AU - Knorr, Christoph ID - 3364 TI - Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten ER - TY - JOUR AU - Torresen, Jim AU - Plessl, Christian AU - Yao, Xin ID - 1772 IS - 7 JF - IEEE Computer KW - self-awareness KW - self-expression TI - Self-Aware and Self-Expressive Systems – Guest Editor's Introduction VL - 48 ER - TY - GEN AU - Ahmed, Abdullah Fathi ID - 10615 TI - Self-Optimizing Organic Cache ER - TY - THES AB - The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies. AU - Beisel, Tobias ID - 10624 SN - 978-3-8325-4155-2 TI - Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing ER - TY - GEN AU - Hangmann, Hendrik ID - 10668 TI - Evolution of Heat Flow Prediction Models for FPGA Devices ER - TY - GEN AU - Haupt, Christian ID - 10671 TI - Computer Vision basierte Klassifikation von HD EMG Signalen ER - TY - CONF AU - Ho, Nam AU - Ahmed, Abdullah Fathi AU - Kaufmann, Paul AU - Platzner, Marco ID - 10673 KW - cache storage KW - field programmable gate arrays KW - multiprocessing systems KW - parallel architectures KW - reconfigurable architectures KW - FPGA KW - dynamic reconfiguration KW - evolvable cache mapping KW - many-core architecture KW - memory-to-cache address mapping function KW - microarchitectural optimization KW - multicore architecture KW - nature-inspired optimization KW - parallelization degrees KW - processor KW - reconfigurable cache mapping KW - reconfigurable computing KW - Field programmable gate arrays KW - Software KW - Tuning T2 - Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) TI - Microarchitectural optimization by means of reconfigurable and evolvable cache mappings ER - TY - CONF AU - Kaufmann, Paul AU - Shen, Cong ID - 10693 T2 - Genetic and Evolutionary Computation (GECCO) TI - Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing ER - TY - CONF AU - Meisner, Sebastian AU - Platzner, Marco ID - 10711 T2 - Field Programmable Technology (FPT), 2015 International Conference on TI - Comparison of thread signatures for error detection in hybrid multi-cores ER - TY - GEN AU - Meißner, Roland ID - 10714 TI - Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs ER - TY - GEN AU - Posewsky, Thorbjörn ID - 10726 TI - Acceleration of Artificial Neural Networks on a Zynq Platform ER - TY - BOOK AU - M. Mora, Antonio AU - Squillero, Giovanni AU - Agapitos, Alexandros AU - Burelli, Paolo AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10757 TI - Applications of Evolutionary Computation - 18th European Conference, EvoApplications VL - 9028 ER - TY - CONF AU - H.W. Leong, Philip AU - Amano, Hideharu AU - Anderson, Jason AU - Bertels, Koen AU - M.P. Cardoso, Jo\~ao AU - Diessel, Oliver AU - Gogniat, Guy AU - Hutton, Mike AU - Lee, JunKyu AU - Luk, Wayne AU - Lysaght, Patrick AU - Platzner, Marco AU - K. Prasanna, Viktor AU - Rissa, Tero AU - Silvano, Cristina AU - So, Hayden AU - Wang, Yu ID - 10765 T2 - Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) TI - Significant papers from the first 25 years of the FPL conference ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10767 T2 - Proceedings of the 29th European Simulation and Modelling Conference (ESM) TI - New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software ER - TY - JOUR AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10770 IS - 6 JF - IEEE Transactions on Nanotechnology TI - From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires VL - 14 ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Zhang, Jian AU - De Micheli, Giovanni AU - Sanchez, Eduardo AU - Reorda, Matteo Sonza ID - 10771 T2 - 2015 IEEE Computer Society Annual Symposium on VLSI TI - On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10772 T2 - Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition TI - Fault modeling in controllable polarity silicon nanowire circuits ER - TY - CONF AU - Guettatfi, Zakarya AU - Kermia, Omar AU - Khouas, Abdelhakim ID - 10779 KW - embedded systems KW - field programmable gate arrays KW - operating systems (computers) KW - scheduling KW - μC/OS-II KW - FPGAs KW - OS foundation KW - SafeRTOS KW - Xenomai KW - chip utilization ration KW - complex time constraints KW - embedded systems KW - hard real-time hardware task allocation KW - hard real-time hardware task scheduling KW - hardware-software real-time operating systems KW - partially reconfigurable field-programmable gate arrays KW - resource constraints KW - safety-critical RTOS KW - Field programmable gate arrays KW - Hardware KW - Job shop scheduling KW - Real-time systems KW - Shape KW - Software SN - 1946-147X T2 - 25th International Conference on Field Programmable Logic and Applications (FPL) TI - Over effective hard real-time hardware tasks scheduling and allocation ER -