TY - GEN AU - Niklas, Jörg ID - 10718 TI - Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme ER - TY - GEN AU - Östermann, Marco ID - 10721 TI - Raytracing on a Custom Instruction Set CPU ER - TY - GEN AU - Westerheide, Nico ID - 10751 TI - Design and Evaluation of MicroBlaze Multi-core Architectures ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Tabkhi, Hamed AU - Miremadi, Seyed Ghassem AU - Ejlali, Alireza ID - 10778 T2 - 2008 International Conference on Microelectronics TI - A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13629 T2 - Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS) TI - Realizing Reconfigurable Mesh Algorithms on Softcore Arrays ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13630 T2 - Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Communication and Synchronization in Multithreaded Reconfigurable Computing Systems ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13631 SN - 9781424419609 T2 - Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL) TI - A portable abstraction layer for hardware threads ER - TY - CONF AU - Schumacher, Tobias AU - Meiche, Robert AU - Kaufmann, Paul AU - Lübbers, Enno AU - Plessl, Christian AU - Platzner, Marco ID - 2364 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Hardware Accelerator for k-th Nearest Neighbor Thinning ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2372 KW - IMORC KW - IP core KW - interconnect T2 - Many-core and Reconfigurable Supercomputing Conference (MRSC) TI - IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers ER - TY - CONF AB - In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits. AU - Kaufmann, Paul AU - Platzner, Marco ID - 6508 KW - integrated circuit design KW - hardware evolution KW - evolutionary hardware design KW - evolutionary optimizers KW - hash functions KW - preengineered circuits KW - Hardware KW - Circuits KW - Design optimization KW - Visualization KW - Genetic programming KW - Genetic mutations KW - Clustering algorithms KW - Biological cells KW - Field programmable gate arrays KW - Routing SN - 076952866X T2 - Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) TI - MOVES: A Modular Framework for Hardware Evolution ER - TY - GEN AU - Beisel, Tobias ID - 10623 TI - Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen ER - TY - JOUR AU - Bergmann, Neil AU - Platzner, Marco AU - Teich, Jürgen ID - 10625 JF - {EURASIP} Journal on Embedded Systems TI - Dynamically Reconfigurable Architectures (editorial) VL - 2007 ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10643 TI - Distributed Simulation of mobile Robots using EyeSim ER - TY - JOUR AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 10646 IS - 4 JF - IET Computers Digital Techniques KW - reconfigurable architectures KW - resource allocation KW - device reconfiguration time KW - dynamic hardware reconfiguration KW - dynamically reconfigurable hardware KW - light-weight runtime system KW - merge server distribute load KW - periodic real-time tasks KW - runtime system overheads KW - schedulability analysis KW - scheduling technique KW - server-based execution KW - synthesis tool flow SN - 1751-8601 TI - Server-based execution of periodic tasks on dynamically reconfigurable hardware VL - 1 ER - TY - GEN AU - Defo, Bertrand ID - 10647 TI - A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization ER - TY - GEN AU - Döhre, Sven ID - 10648 TI - Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10689 T2 - Architecture of Computing Systems (ARCS) TI - Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution VL - 4415 ER - TY - GEN AU - Meiche, Robert ID - 10709 TI - VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen ER - TY - GEN AU - Reisch, Waldemar ID - 10728 TI - Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS ER - TY - GEN AU - Rethmeier, Eike ID - 10729 TI - Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem ER -