TY - GEN AU - Beisel, Tobias ID - 10623 TI - Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen ER - TY - JOUR AU - Bergmann, Neil AU - Platzner, Marco AU - Teich, Jürgen ID - 10625 JF - {EURASIP} Journal on Embedded Systems TI - Dynamically Reconfigurable Architectures (editorial) VL - 2007 ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10643 TI - Distributed Simulation of mobile Robots using EyeSim ER - TY - JOUR AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 10646 IS - 4 JF - IET Computers Digital Techniques KW - reconfigurable architectures KW - resource allocation KW - device reconfiguration time KW - dynamic hardware reconfiguration KW - dynamically reconfigurable hardware KW - light-weight runtime system KW - merge server distribute load KW - periodic real-time tasks KW - runtime system overheads KW - schedulability analysis KW - scheduling technique KW - server-based execution KW - synthesis tool flow SN - 1751-8601 TI - Server-based execution of periodic tasks on dynamically reconfigurable hardware VL - 1 ER - TY - GEN AU - Defo, Bertrand ID - 10647 TI - A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization ER - TY - GEN AU - Döhre, Sven ID - 10648 TI - Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10689 T2 - Architecture of Computing Systems (ARCS) TI - Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution VL - 4415 ER - TY - GEN AU - Meiche, Robert ID - 10709 TI - VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen ER - TY - GEN AU - Reisch, Waldemar ID - 10728 TI - Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS ER - TY - GEN AU - Rethmeier, Eike ID - 10729 TI - Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem ER - TY - CONF AU - Schumacher, Tobias AU - Lübbers, Enno AU - Kaufmann, Paul AU - Platzner, Marco ID - 10735 T2 - Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) TI - Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster VL - 15 ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13627 SN - 9781424410590 T2 - Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) TI - A Many-Core Implementation Based on the Reconfigurable Mesh Model ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13628 SN - 9781424410590 T2 - Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) TI - ReconOS: An RTOS Supporting Hard-and Software Threads ER - TY - CONF AB - This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. AU - Plessl, Christian AU - Platzner, Marco AU - Thiele, Lothar ID - 2401 KW - temporal partitioning KW - retiming KW - ILP T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - Optimal Temporal Partitioning based on Slowdown and Retiming ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10688 T2 - Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD) TI - Multi-objective Intrinsic Hardware Evolution ER - TY - GEN AU - Mühlenbernd, Roland ID - 10716 TI - FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks ER - TY - CONF AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 13624 T2 - Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) TI - Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13625 T2 - In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) TI - An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13626 T2 - Proceedings of the 13th Reconfigurable Architectures Workshop (RAW) TI - Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware ER - TY - CONF AB - This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. AU - Plessl, Christian AU - Platzner, Marco ID - 2411 KW - Zippy T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Zippy – A coarse-grained reconfigurable array with support for hardware virtualization ER -