TY - CONF AU - Hansmeier, Tim AU - Platzner, Marco ID - 21813 SN - 978-1-4503-8351-6 T2 - GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS ER - TY - JOUR AB - Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques. AU - Jakobs, Marie-Christine AU - Pauck, Felix AU - Platzner, Marco AU - Wehrheim, Heike AU - Wiersema, Tobias ID - 27841 JF - IEEE Access KW - Software Analysis KW - Abstract Interpretation KW - Custom Instruction KW - Hardware Verification TI - Software/Hardware Co-Verification for Custom Instruction Set Processors ER - TY - CONF AU - Ahmed, Qazi Arbab ID - 29138 T2 - 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC) TI - Hardware Trojans in Reconfigurable Computing ER - TY - CONF AB - The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques. AU - Ahmed, Qazi Arbab AU - Wiersema, Tobias AU - Platzner, Marco ID - 20681 T2 - 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Malicious Routing: Circumventing Bitstream-level Verification for FPGAs ER - TY - CONF AU - Clausing, Lennart ID - 30909 T2 - Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Jentzsch, Felix AU - Kuschel, Maurice AU - Arshad, Rahil AU - Rautmare, Sneha AU - Manjunatha, Suraj AU - Platzner, Marco AU - Boschmann, Alexander AU - Schollbach, Dirk ID - 30908 T2 - Machine Learning and Principles and Practice of Knowledge Discovery in Databases TI - FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics ER - TY - CONF AU - Guetttatfi, Zakarya AU - Kaufmann, Paul AU - Platzner, Marco ID - 3583 T2 - Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC) TI - Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices ER - TY - GEN AU - Chandrakar, Khushboo ID - 21324 TI - Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis ER - TY - GEN AB - Robots are becoming increasingly autonomous and more capable. Because of a limited portable energy budget by e.g. batteries, and more demanding algorithms, an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs) for example can provide fast and efficient processing and the Robot Operating System (ROS) is a popular middleware used for robotic applications. The novel ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework for integrating reconfigurable hardware. It provides a unified interface between software and hardware. ReconROS is evaluated in this thesis by implementing a Sobel filter as the video processing application, running on a Zynq-7000 series System on Chip. Timing measurements were taken of execution and transfer times and were compared to theoretical values. Designing the hardware implementation is done by C code using High Level Synthesis and with the interface and functionality provided by ReconROS. An important aspect is the publish/subscribe mechanism of ROS. The Operating System interface functions for publishing and subscribing are reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces consistency to the execution times and performs twice as fast as the software implementation. AU - Henke, Luca-Sebastian ID - 21432 TI - Evaluation of a ReconOS-ROS Combination based on a Video Processing Application ER - TY - CONF AU - Gatica, Carlos Paiz AU - Platzner, Marco ID - 21584 SN - 2522-8579 T2 - Machine Learning for Cyber Physical Systems (ML4CPS 2017) TI - Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures ER - TY - JOUR AB - Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 17358 IS - 9 JF - IEEE Transactions On Very Large Scale Integration Systems KW - Approximate circuit synthesis KW - approximate computing KW - error metrics KW - formal verification KW - proof-carrying hardware SN - 1063-8210 TI - Proof-carrying Approximate Circuits VL - 28 ER - TY - JOUR AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 17369 JF - International Journal of Hybrid intelligent Systems TI - Evolution of Application-Specific Cache Mappings ER - TY - GEN AB - On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies. In the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. In this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification. In our experimental results, we present the runtimes of our approach. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 20748 T2 - Fifth Workshop on Approximate Computing (AxC 2020) TI - Search Space Characterization for AxC Synthesis ER - TY - CONF AU - Lienen, Christian AU - Platzner, Marco AU - Rinner, Bernhard ID - 20750 T2 - Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT) TI - ReconROS: Flexible Hardware Acceleration for ROS2 Applications ER - TY - GEN AU - Thiele, Simon ID - 20820 TI - Implementing Machine Learning Functions as PYNQ FPGA Overlays ER - TY - GEN AU - Jaganath, Vivek ID - 20821 TI - Extension and Evaluation of Python-based High-Level Synthesis Tool Flows ER - TY - CONF AU - Hansmeier, Tim AU - Kaufmann, Paul AU - Platzner, Marco ID - 17063 SN - 978-1-4503-7127-8 T2 - GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - An Adaption Mechanism for the Error Threshold of XCSF ER - TY - JOUR AB - Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application. AU - Anwer, Jahanzeb AU - Meisner, Sebastian AU - Platzner, Marco ID - 17092 JF - International Journal of Reconfigurable Computing SN - 1687-7195 TI - Dynamic Reliability Management for FPGA-Based Systems ER - TY - JOUR AU - Bellman, K. AU - Dutt, N. AU - Esterle, L. AU - Herkersdorf, A. AU - Jantsch, A. AU - Landauer, C. AU - R. Lewis, P. AU - Platzner, Marco AU - TaheriNejad, N. AU - Tammemäe, K. ID - 15836 JF - ACM Transactions on Cyber-Physical Systems TI - Self-aware Cyber-Physical Systems VL - Accepted for Publication ER - TY - CONF AB - Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 16213 T2 - Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 TI - A Hybrid Synthesis Methodology for Approximate Circuits ER -