TY - GEN AU - Schnuer, Jan-Philip ID - 3365 TI - Static Scheduling Algorithms for Heterogeneous Compute Nodes ER - TY - GEN AU - Croce, Marcel ID - 3366 TI - Evaluation of OpenCL-based Compilation for FPGAs ER - TY - CONF AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Andrews, David ID - 3373 SN - 0302-9743 T2 - ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications TI - An FPGA/HMC-Based Accelerator for Resolution Proof Checking VL - 10824 ER - TY - GEN AB - Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Ghasemzadeh Mohammadi, Hassan AU - Awais, Muhammad AU - Platzner, Marco ID - 3586 KW - Approximate Computing KW - Framework KW - Pareto Front KW - Accuracy T2 - Third Workshop on Approximate Computing (AxC 2018) TI - CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation ER - TY - THES AB - Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches. AU - Ho, Nam ID - 3720 TI - FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization ER - TY - GEN AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 1165 T2 - 4th Workshop On Approximate Computing (WAPCO 2018) TI - Making the Case for Proof-carrying Approximate Circuits ER - TY - CONF AU - Lösch, Achim AU - Platzner, Marco ID - 5547 SN - 9781538674796 T2 - 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes ER - TY - CONF AB - Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 10598 KW - Approximate computing KW - High-level synthesis KW - Accuracy KW - Monte-Carlo tree search KW - Circuit simulation T2 - 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) TI - An MCTS-based Framework for Synthesis of Approximate Circuits ER - TY - GEN AU - Clausing, Lennart ID - 10782 TI - Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data ER - TY - GEN AU - Jentzsch, Felix Paul ID - 1097 KW - Approximate Computing KW - Proof-Carrying Hardware KW - Formal Verification TI - Enforcing IP Core Connection Properties with Verifiable Security Monitors ER - TY - JOUR AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Li, Zhiwu AU - Alnowibet, Khalid AU - Platzner, Marco ID - 12965 JF - IEEE Access SN - 2169-3536 TI - R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints ER - TY - GEN AU - Hansmeier, Tim ID - 3580 TI - An FPGA Accelerator for Checking Resolution Proofs ER - TY - GEN AU - Witschen, Linus Matthias ID - 1157 TI - A Framework for the Synthesis of Approximate Circuits ER - TY - GEN AU - Knorr, Christoph ID - 74 TI - OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten ER - TY - JOUR AB - This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network. AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 9919 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) KW - Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies VL - 94 ER - TY - CONF AB - Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules. AU - Lösch, Achim AU - Platzner, Marco ID - 65 T2 - Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements ER - TY - JOUR AB - Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits. AU - Isenberg, Tobias AU - Platzner, Marco AU - Wehrheim, Heike AU - Wiersema, Tobias ID - 68 IS - 4 JF - ACM Transactions on Design Automation of Electronic Systems TI - Proof-Carrying Hardware via Inductive Invariants ER - TY - JOUR AU - H.W. Leong, Philip AU - Amano, Hideharu AU - Anderson, Jason AU - Bertels, Koen AU - M.P. Cardoso, Jo\~{a}o AU - Diessel, Oliver AU - Gogniat, Guy AU - Hutton, Mike AU - Lee, JunKyu AU - Luk, Wayne AU - Lysaght, Patrick AU - Platzner, Marco AU - K. Prasanna, Viktor AU - Rissa, Tero AU - Silvano, Cristina AU - So, Hayden AU - Wang, Yu ID - 10600 JF - ACM Transactions on Reconfigurable Technology and Systems TI - The First 25 Years of the FPL Conference – Significant Papers ER - TY - JOUR AU - F. DeMara, Ronald AU - Platzner, Marco AU - Ottavi, Marco ID - 10601 JF - IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing TI - Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial) ER - TY - JOUR AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10611 JF - Microprocessors and Microsystems TI - Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus ER -