TY - GEN AU - Kaltschmidt, Christian ID - 10613 TI - An AR-based Training and Assessment System for Myoelectrical Prosthetic Control ER - TY - CONF AU - Boschmann, Alexander AU - Thombansen, Georg AU - Witschen, Linus Matthias AU - Wiens, Alex AU - Platzner, Marco ID - 10630 T2 - Design, Automation and Test in Europe (DATE) TI - A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller ER - TY - GEN AU - Riaz, Umair ID - 10666 TI - Acceleration of Industrial Analytics Functions on a Platform FPGA ER - TY - CONF AU - Ho, Nam AU - Ashraf, Ishraq Ibne AU - Kaufmann, Paul AU - Platzner, Marco ID - 10672 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10676 KW - Linux KW - cache storage KW - microprocessor chips KW - multiprocessing systems KW - LEON3-Linux based multicore processor KW - MiBench suite KW - block sizes KW - cache adaptation KW - evolvable caches KW - memory-to-cache-index mapping function KW - processor caches KW - reconfigurable cache mapping optimization KW - reconfigurable hardware technology KW - replacement strategies KW - standard Linux OS KW - time a complete hardware implementation KW - Hardware KW - Indexes KW - Linux KW - Measurement KW - Multicore processing KW - Optimization KW - Training T2 - 2017 International Conference on Field Programmable Technology (ICFPT) TI - Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10692 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies ER - TY - GEN AU - Dietrich, Andreas ID - 10708 TI - Reconfigurable Cryptographic Services ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10740 JF - The Journal of Engineering TI - Fast Network Restoration by Partitioning of Parallel Black Start Zones ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10759 TI - Applications of Evolutionary Computation - 20th European Conference, EvoApplications ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10760 T2 - KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI TI - Parametrizing Cartesian Genetic Programming: An Empirical Study ER - TY - CONF AU - Kaufmann, Paul AU - Ho, Nam AU - Platzner, Marco ID - 10761 T2 - Adaptive Hardware and Systems (AHS) TI - Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10762 T2 - Genetic and Evolutionary Computation (GECCO), Compendium TI - An Empirical Study on the Parametrization of Cartesian Genetic Programming ER - TY - CONF AU - Guettatfi, Zakarya AU - Hübner, Philipp AU - Platzner, Marco AU - Rinner, Bernhard ID - 10780 KW - embedded systems KW - image sensors KW - power aware computing KW - wireless sensor networks KW - Zynq-based VSN node prototype KW - computational self-awareness KW - design approach KW - platform levels KW - power consumption KW - visual sensor networks KW - visual sensor nodes KW - Cameras KW - Hardware KW - Middleware KW - Multicore processing KW - Operating systems KW - Runtime KW - Reconfigurable platforms KW - distributed embedded systems KW - performance-resource trade-off KW - self-awareness KW - visual sensor nodes T2 - 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Computational self-awareness as design approach for visual sensor nodes ER - TY - CONF AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Platzner, Marco ID - 14893 SN - 1865-0929 T2 - Communications in Computer and Information Science TI - I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems ER - TY - JOUR AB - Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved. AU - Wiersema, Tobias AU - Bockhorn, Arne AU - Platzner, Marco ID - 222 JF - Computers & Electrical Engineering TI - An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 5812 SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - GEN AU - Cedric Mertens, Jan ID - 10612 TI - Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion ER - TY - GEN AU - Nassery, Abdul Sami ID - 10616 TI - Implementation of Bilinear Pairings on Reconfigurable Hardware ER - TY - GEN AU - Amin, Omair ID - 10617 TI - Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10622 T2 - Euromicro Conference on Digital System Design (DSD) TI - Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs ER - TY - CONF AU - Boschmann, Alexander AU - Dosen, Strahinja AU - Werner, Andreas AU - Raies, Ali AU - Farina, Dario ID - 10631 T2 - Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI) TI - A novel immersive augmented reality system for prosthesis training and assessment ER - TY - JOUR AU - Graf, Tobias AU - Platzner, Marco ID - 10661 JF - Journal Theoretical Computer Science TI - Adaptive playouts for online learning of policies during Monte Carlo Tree Search VL - 644 ER - TY - GEN AU - Horstmann, Jens ID - 10695 TI - Beschleunigte Simulation elektrischer Stromnetze mit GPUs ER - TY - JOUR AU - Ma, Chenjie AU - Kaufmann, Paul AU - Töbermann, J.-Christian AU - Braun, Martin ID - 10705 IS - (part 2) JF - Renewable Energy TI - Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control VL - 87 ER - TY - GEN AU - Makeswaran, Vignesh ID - 10706 TI - Operating System Support for Reconfigurable Cache ER - TY - GEN AU - Ibne Ashraf, Ishraq ID - 10707 TI - Private/Shared Data Classification and Implementation for a Multi-Softcore Platform ER - TY - CONF AU - Meisner, Sebastian AU - Platzner, Marco ID - 10712 T2 - Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on TI - Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level ER - TY - GEN AU - Schmidt, Marco ID - 10755 TI - Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10758 TI - Applications of Evolutionary Computation - 19th European Conference, EvoApplications VL - 9597 ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10766 T2 - Proceedings of the 30th European Simulation and Modelling Conference (ESM) TI - RCo-Design: New Visual Environment for Reconfigurable Embedded Systems ER - TY - CONF AU - Ghribi, Ines AU - Ben Abdallah, Riadh AU - Khalgui, Mohamed AU - Platzner, Marco ID - 10768 T2 - Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) TI - New Co-design Methodology for Real-time Embedded Systems ER - TY - JOUR AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - De Micheli, Giovanni ID - 10769 IS - 99 JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems TI - Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation VL - PP ER - TY - GEN AU - Hermansen, Sven ID - 10781 TI - Custom Memory Controller for ReconOS ER - TY - BOOK AB - Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering. ED - Lewis, Peter R. ED - Platzner, Marco ED - Rinner, Bernhard ED - Tørresen, Jim ED - Yao, Xin ID - 12972 SN - 1619-7127 TI - Self-aware Computing Systems: An Engineering Approach ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus Matthias AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 15873 KW - Electromyography KW - Feature extraction KW - Delays KW - Hardware Pattern recognition KW - Prosthetics KW - High definition video SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13151 T2 - Computer and Games TI - Using Deep Convolutional Neural Networks in Monte Carlo Tree Search ER - TY - CONF AU - Graf, Tobias AU - Platzner, Marco ID - 13152 T2 - IEEE Computational Intelligence and Games TI - Monte-Carlo Simulation Balancing Revisited ER - TY - CONF AB - Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module. AU - Wiersema, Tobias AU - Platzner, Marco ID - 132 T2 - Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) TI - Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware ER - TY - CHAP AB - In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. AU - Agne, Andreas AU - Platzner, Marco AU - Plessl, Christian AU - Happe, Markus AU - Lübbers, Enno ED - Koch, Dirk ED - Hannig, Frank ED - Ziener, Daniel ID - 29 SN - 978-3-319-26406-6 T2 - FPGAs for Software Programmers TI - ReconOS ER - TY - CHAP AB - Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 156 T2 - Self-aware Computing Systems TI - Self-aware Compute Nodes ER - TY - CONF AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. AU - Lösch, Achim AU - Beisel, Tobias AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 168 T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center ER - TY - CONF AB - Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level. AU - Wiersema, Tobias AU - Wu, Sen AU - Platzner, Marco ID - 269 T2 - Proceedings of the International Symposium in Reconfigurable Computing (ARC) TI - On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach ER - TY - GEN AU - Knorr, Christoph ID - 3364 TI - Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten ER - TY - JOUR AU - Torresen, Jim AU - Plessl, Christian AU - Yao, Xin ID - 1772 IS - 7 JF - IEEE Computer KW - self-awareness KW - self-expression TI - Self-Aware and Self-Expressive Systems – Guest Editor's Introduction VL - 48 ER - TY - GEN AU - Ahmed, Abdullah Fathi ID - 10615 TI - Self-Optimizing Organic Cache ER - TY - THES AB - The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies. AU - Beisel, Tobias ID - 10624 SN - 978-3-8325-4155-2 TI - Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing ER - TY - GEN AU - Hangmann, Hendrik ID - 10668 TI - Evolution of Heat Flow Prediction Models for FPGA Devices ER - TY - GEN AU - Haupt, Christian ID - 10671 TI - Computer Vision basierte Klassifikation von HD EMG Signalen ER - TY - CONF AU - Ho, Nam AU - Ahmed, Abdullah Fathi AU - Kaufmann, Paul AU - Platzner, Marco ID - 10673 KW - cache storage KW - field programmable gate arrays KW - multiprocessing systems KW - parallel architectures KW - reconfigurable architectures KW - FPGA KW - dynamic reconfiguration KW - evolvable cache mapping KW - many-core architecture KW - memory-to-cache address mapping function KW - microarchitectural optimization KW - multicore architecture KW - nature-inspired optimization KW - parallelization degrees KW - processor KW - reconfigurable cache mapping KW - reconfigurable computing KW - Field programmable gate arrays KW - Software KW - Tuning T2 - Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) TI - Microarchitectural optimization by means of reconfigurable and evolvable cache mappings ER - TY - CONF AU - Kaufmann, Paul AU - Shen, Cong ID - 10693 T2 - Genetic and Evolutionary Computation (GECCO) TI - Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing ER -