TY - JOUR AB - The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications AU - Agne, Andreas AU - Happe, Markus AU - Keller, Ariane AU - Lübbers, Enno AU - Plattner, Bernhard AU - Platzner, Marco AU - Plessl, Christian ID - 328 IS - 1 JF - IEEE Micro TI - ReconOS - An Operating System Approach for Reconfigurable Computing VL - 34 ER - TY - CONF AU - C. Durelli, Gianluca AU - Pogliani, Marcello AU - Miele, Antonio AU - Plessl, Christian AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1778 T2 - Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) TI - Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach ER - TY - CONF AB - Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian ID - 439 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Deferring Accelerator Offloading Decisions to Application Runtime ER - TY - CONF AB - Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 406 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Kernel-Centric Acceleration of High Accuracy Stereo-Matching ER - TY - CONF AU - C. Durelli, Gianluca AU - Copolla, Marcello AU - Djafarian, Karim AU - Koranaros, George AU - Miele, Antonio AU - Paolino, Michele AU - Pell, Oliver AU - Plessl, Christian AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1780 T2 - Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC) TI - SAVE: Towards efficient resource management in heterogeneous system architectures ER - TY - JOUR AU - Giefers, Heiner AU - Plessl, Christian AU - Förstner, Jens ID - 1779 IS - 5 JF - ACM SIGARCH Computer Architecture News KW - funding-maxup KW - tet_topic_hpc SN - 0163-5964 TI - Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers VL - 41 ER - TY - THES AB - Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches. AU - Kaufmann, Paul ID - 11619 SN - 978-3-8325-3530-8 TI - Adapting Hardware Systems by Means of Multi-Objective Evolution ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 1786 T2 - Proc. IEEE Signal Processing and Communications Conf. (SUI) TI - FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm ER - TY - JOUR AU - Kasap, Server AU - Redif, Soydan ID - 1792 IS - 3 JF - IEEE Trans. on Very Large Scale Integration (VLSI) Systems TI - Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices VL - 22 ER - TY - THES AB - Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. AU - Happe, Markus ID - 501 SN - 978-3-8325-3425-7 TI - Performance and thermal management on self-adaptive hybrid multi-cores ER - TY - JOUR AU - Happe, Markus AU - Lübbers, Enno AU - Platzner, Marco ID - 10604 IS - 1 JF - International Journal of Real-time Image Processing TI - A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking VL - 8 ER - TY - CONF AU - Anwer, Jahanzeb AU - Meisner, Sebastian AU - Platzner, Marco ID - 10620 KW - fault tolerant computing KW - field programmable gate arrays KW - logic design KW - reliability KW - BYU-LANL tool KW - DRM tool flow KW - FPGA based hardware designs KW - avionic application KW - device technologies KW - dynamic reliability management KW - fault-tolerant operation KW - hardware designs KW - reconfiguring reliability levels KW - space applications KW - Field programmable gate arrays KW - Hardware KW - Redundancy KW - Reliability engineering KW - Runtime KW - Tunneling magnetoresistance T2 - Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on TI - Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime ER - TY - GEN AU - Bick, Christian ID - 10626 TI - Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner ER - TY - CONF AU - Boschmann, Alexander AU - Nofen, Barbara AU - Platzner, Marco ID - 10634 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10635 T2 - Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC) TI - Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array ER - TY - CONF AU - Glette, Kyrre AU - Kaufmann, Paul AU - Assad, Christopher AU - Wolf, Michael ID - 10655 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface VL - 1 ER - TY - BOOK AU - Kaufmann, Paul ID - 10681 TI - Adapting Hardware Systems by Means of Multi-Objective Evolution ER - TY - JOUR AU - Kaufmann, Paul AU - Glette, Kyrre AU - Gruber, Tiemo AU - Platzner, Marco AU - Torresen, Jim AU - Sick, Bernhard ID - 10684 IS - 1 JF - IEEE Transactions on Evolutionary Computation TI - Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers VL - 17 ER - TY - GEN AU - Knoop, Michael ID - 10700 TI - Behavior Models for Electric Vehicles ER - TY - GEN AU - Nofen, Barbara ID - 10720 TI - Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors ER - TY - GEN AU - Pudelko, Daniel ID - 10727 TI - Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs ER - TY - GEN AU - Riebler, Heinrich ID - 10730 TI - Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs ER - TY - GEN AU - Sprenger, Alexander ID - 10741 TI - MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung ER - TY - GEN AU - Steppeler, Philipp ID - 10743 TI - Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen ER - TY - CONF AU - Toebermann, Christian AU - Geibel, Daniel AU - Hau, Manuel AU - Brandl, Ron AU - Kaufmann, Paul AU - Ma, Chenjie AU - Braun, Martin AU - Degner, Tobias ID - 10745 T2 - Real-Time Conference TI - Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Yazdani, Majid AU - De Micheli, Giovanni ID - 10774 T2 - 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) TI - A fast TCAD-based methodology for Variation analysis of emerging nano-devices ER - TY - CONF AU - Gaillardon, Pierre-Emmanuel AU - Ghasemzadeh Mohammadi, Hassan AU - De Micheli, Giovanni ID - 10775 T2 - 2013 14th Latin American Test Workshop-LATW TI - Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study ER - TY - CONF AU - Graf, Tobias AU - Schäfers, Lars AU - Platzner, Marco ID - 13645 T2 - Proceedings of the International Conference on Computers and Games (CG) TI - On Semeai Detection in Monte-Carlo Go. ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - JOUR AU - Thielemans, Kris AU - Tsoumpas, Charalampos AU - Mustafovic, Sanida AU - Beisel, Tobias AU - Aguiar, Pablo AU - Dikaios, Nikolaos AU - W Jacobson, Matthew ID - 2172 IS - 4 JF - Physics in Medicine and Biology TI - STIR: Software for Tomographic Image Reconstruction Release 2 VL - 57 ER - TY - JOUR AU - Redif, Soydan AU - Kasap, Server ID - 2173 IS - 12 JF - Int. Journal of Electronics TI - Parallel algorithm for computation of second-order sequential best rotations VL - 100 ER - TY - JOUR AU - Kasap, Server AU - Benkrid, Khaled ID - 2174 IS - 6 JF - Journal of Computers TI - Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer VL - 7 ER - TY - THES AB - FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety. AU - Drzevitzky, Stephanie ID - 586 TI - Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security ER - TY - GEN AU - Plessl, Christian AU - Platzner, Marco AU - Agne, Andreas AU - Happe, Markus AU - Lübbers, Enno ID - 587 TI - Programming models for reconfigurable heterogeneous multi-cores ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10636 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array ER - TY - GEN AU - Dridger, Denis ID - 10650 TI - Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer ER - TY - THES AB - The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores. The book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores. AU - Giefers, Heiner ID - 10652 SN - 978-3-8325-3165-2 TI - Design and Programming of Reconfigurable Mesh based Many-Cores ER - TY - GEN AU - Graf, Tobias ID - 10658 TI - Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go ER - TY - GEN AU - Hangmann, Hendrik ID - 10667 TI - Generating Adjustable Temperature Gradients on modern FPGAs ER - TY - JOUR AU - Kaufmann, Paul AU - Glette, Kyrre AU - Platzner, Marco AU - Torresen, Jim ID - 10685 IS - 4 JF - International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) TI - Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture VL - 3 ER - TY - GEN AU - Platzner, Marco AU - Boschmann, Alexander AU - Kaufmann, Paul ID - 10723 TI - Wieder natürlich gehen und greifen ER - TY - GEN AU - Schmitz, Henning ID - 10734 TI - Stereo Matching on a HC-1 Hybrid Core Computer ER - TY - GEN AU - Topmöller, Christoph ID - 10747 TI - Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System ER - TY - GEN AU - Wistuba, Martin ID - 10754 TI - Analysis of Pattern Based Model Design and Learning in Computer-Go ER - TY - GEN AU - Lewis, Peter AU - Platzner, Marco AU - Yao, Xin ID - 13462 TI - An outlook for self-awareness in computing systems ER -