TY - GEN AU - Pudelko, Daniel ID - 10727 TI - Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs ER - TY - GEN AU - Riebler, Heinrich ID - 10730 TI - Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs ER - TY - GEN AU - Sprenger, Alexander ID - 10741 TI - MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung ER - TY - GEN AU - Steppeler, Philipp ID - 10743 TI - Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen ER - TY - CONF AU - Toebermann, Christian AU - Geibel, Daniel AU - Hau, Manuel AU - Brandl, Ron AU - Kaufmann, Paul AU - Ma, Chenjie AU - Braun, Martin AU - Degner, Tobias ID - 10745 T2 - Real-Time Conference TI - Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Gaillardon, Pierre-Emmanuel AU - Yazdani, Majid AU - De Micheli, Giovanni ID - 10774 T2 - 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) TI - A fast TCAD-based methodology for Variation analysis of emerging nano-devices ER - TY - CONF AU - Gaillardon, Pierre-Emmanuel AU - Ghasemzadeh Mohammadi, Hassan AU - De Micheli, Giovanni ID - 10775 T2 - 2013 14th Latin American Test Workshop-LATW TI - Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study ER - TY - CONF AU - Graf, Tobias AU - Schäfers, Lars AU - Platzner, Marco ID - 13645 T2 - Proceedings of the International Conference on Computers and Games (CG) TI - On Semeai Detection in Monte-Carlo Go. ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - JOUR AU - Thielemans, Kris AU - Tsoumpas, Charalampos AU - Mustafovic, Sanida AU - Beisel, Tobias AU - Aguiar, Pablo AU - Dikaios, Nikolaos AU - W Jacobson, Matthew ID - 2172 IS - 4 JF - Physics in Medicine and Biology TI - STIR: Software for Tomographic Image Reconstruction Release 2 VL - 57 ER - TY - JOUR AU - Redif, Soydan AU - Kasap, Server ID - 2173 IS - 12 JF - Int. Journal of Electronics TI - Parallel algorithm for computation of second-order sequential best rotations VL - 100 ER - TY - JOUR AU - Kasap, Server AU - Benkrid, Khaled ID - 2174 IS - 6 JF - Journal of Computers TI - Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer VL - 7 ER - TY - THES AB - FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety. AU - Drzevitzky, Stephanie ID - 586 TI - Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security ER - TY - GEN AU - Plessl, Christian AU - Platzner, Marco AU - Agne, Andreas AU - Happe, Markus AU - Lübbers, Enno ID - 587 TI - Programming models for reconfigurable heterogeneous multi-cores ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco ID - 10636 T2 - Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) TI - Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array ER - TY - GEN AU - Dridger, Denis ID - 10650 TI - Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer ER - TY - THES AB - The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores. The book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores. AU - Giefers, Heiner ID - 10652 SN - 978-3-8325-3165-2 TI - Design and Programming of Reconfigurable Mesh based Many-Cores ER - TY - GEN AU - Graf, Tobias ID - 10658 TI - Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go ER - TY - GEN AU - Hangmann, Hendrik ID - 10667 TI - Generating Adjustable Temperature Gradients on modern FPGAs ER - TY - JOUR AU - Kaufmann, Paul AU - Glette, Kyrre AU - Platzner, Marco AU - Torresen, Jim ID - 10685 IS - 4 JF - International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) TI - Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture VL - 3 ER - TY - GEN AU - Platzner, Marco AU - Boschmann, Alexander AU - Kaufmann, Paul ID - 10723 TI - Wieder natürlich gehen und greifen ER - TY - GEN AU - Schmitz, Henning ID - 10734 TI - Stereo Matching on a HC-1 Hybrid Core Computer ER - TY - GEN AU - Topmöller, Christoph ID - 10747 TI - Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System ER - TY - GEN AU - Wistuba, Martin ID - 10754 TI - Analysis of Pattern Based Model Design and Learning in Computer-Go ER - TY - GEN AU - Lewis, Peter AU - Platzner, Marco AU - Yao, Xin ID - 13462 TI - An outlook for self-awareness in computing systems ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - JOUR AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2108 IS - 2 JF - Microprocessors and Microsystems KW - funding-altera SN - 0141-9331 TI - IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators VL - 36 ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - JOUR AU - Grad, Mariusz AU - Plessl, Christian ID - 2177 JF - Int. Journal of Reconfigurable Computing (IJRC) TI - On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CHAP AU - Plessl, Christian AU - Platzner, Marco ED - Khalgui, Mohamed ED - Hanisch, Hans-Michael ID - 2202 SN - 978-1-60960-086-0 T2 - Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility TI - Hardware Virtualization on Dynamically Reconfigurable Embedded Processors ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AB - Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach. AU - Drzevitzky, Stephanie AU - Platzner, Marco ID - 666 T2 - Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco ID - 10637 T2 - Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT) TI - Accurate gait phase detection using surface electromyographic signals and support vector machines ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco AU - Robrecht, Michael AU - Hahn, Martin AU - Winkler, Michael ID - 10638 T2 - Proc. MyoElectric Controls Symposium (MEC) TI - Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems ER - TY - GEN AU - Ikonomakis, Nikolaos ID - 10678 TI - PinSim: Schnelle Simulation mit Pintools ER - TY - GEN AU - Kassner, Hendrik ID - 10680 TI - MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern ER - TY - CHAP AU - Kaufmann, Paul AU - Platzner, Marco ED - Müller-Schloer, Christian ED - Schmeck, Hartmut ED - Ungerer, Theo ID - 10687 T2 - Organic Computing---A Paradigm Shift for Complex Systems TI - Multi-objective Intrinsic Evolution of Embedded Systems VL - 1 ER - TY - GEN AU - Schwabe, Arne ID - 10736 TI - Analysis of Algorithmic Approaches for Temporal Partitioning ER - TY - CHAP AU - Sekanina, Lukas AU - Walker, James Alfred AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 10737 T2 - Cartesian Genetic Programming TI - Evolution of Electronic Circuits ER -