TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - JOUR AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2108 IS - 2 JF - Microprocessors and Microsystems KW - funding-altera SN - 0141-9331 TI - IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators VL - 36 ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - JOUR AU - Grad, Mariusz AU - Plessl, Christian ID - 2177 JF - Int. Journal of Reconfigurable Computing (IJRC) TI - On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CHAP AU - Plessl, Christian AU - Platzner, Marco ED - Khalgui, Mohamed ED - Hanisch, Hans-Michael ID - 2202 SN - 978-1-60960-086-0 T2 - Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility TI - Hardware Virtualization on Dynamically Reconfigurable Embedded Processors ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AB - Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach. AU - Drzevitzky, Stephanie AU - Platzner, Marco ID - 666 T2 - Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco ID - 10637 T2 - Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT) TI - Accurate gait phase detection using surface electromyographic signals and support vector machines ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco AU - Robrecht, Michael AU - Hahn, Martin AU - Winkler, Michael ID - 10638 T2 - Proc. MyoElectric Controls Symposium (MEC) TI - Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems ER - TY - GEN AU - Ikonomakis, Nikolaos ID - 10678 TI - PinSim: Schnelle Simulation mit Pintools ER - TY - GEN AU - Kassner, Hendrik ID - 10680 TI - MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern ER - TY - CHAP AU - Kaufmann, Paul AU - Platzner, Marco ED - Müller-Schloer, Christian ED - Schmeck, Hartmut ED - Ungerer, Theo ID - 10687 T2 - Organic Computing---A Paradigm Shift for Complex Systems TI - Multi-objective Intrinsic Evolution of Embedded Systems VL - 1 ER - TY - GEN AU - Schwabe, Arne ID - 10736 TI - Analysis of Algorithmic Approaches for Temporal Partitioning ER - TY - CHAP AU - Sekanina, Lukas AU - Walker, James Alfred AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 10737 T2 - Cartesian Genetic Programming TI - Evolution of Electronic Circuits ER - TY - CHAP AU - Walker, James Alfred AU - Miller, Julian F. AU - Kaufmann, Paul AU - Platzner, Marco ID - 10748 T2 - Cartesian Genetic Programming TI - Problem Decomposition in Cartesian Genetic Programming ER - TY - GEN AU - Welp, Daniel ID - 10750 TI - User Space Scheduling for Heterogeneous Systems ER - TY - CONF AU - Agne, Andreas AU - Platzner, Marco AU - Lübbers, Enno ID - 13643 SN - 9781457714849 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Memory Virtualization for Multithreaded Reconfigurable Hardware ER - TY - CONF AU - Henkel, Jörg AU - Hedrich, Lars AU - Herkersdorf, Andreas AU - Kapitza, Rüdiger AU - Lohmann, Daniel AU - Marwedel, Peter AU - Platzner, Marco AU - Rosenstiel, Wolfgang AU - Schlichtmann, Ulf AU - Spinczyk, Olaf AU - Tahoori, Mehdi AU - Bauer, Lars AU - Teich, Jürgen AU - Wehn, Norbert AU - Wunderlich, Hans-Joachim AU - Becker, Joachim AU - Bringmann, Oliver AU - Brinkschulte, Uwe AU - Chakraborty, Samarjit AU - Engel, Michael AU - Ernst, Rolf AU - Härtig, Hermann ID - 13644 SN - 9781450307154 T2 - Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11 TI - Design and architectures for dependable embedded systems ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - JOUR AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2201 JF - Int. Journal of Recon- figurable Computing (IJRC) KW - funding-altera TI - FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - JOUR AU - Drzevitzky, Stephanie AU - Kastens, Uwe AU - Platzner, Marco ID - 10605 JF - International Journal of Reconfigurable Computing TI - Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification VL - 2010 ER - TY - GEN AU - Agne, Andreas ID - 10614 TI - Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen ER - TY - GEN AU - Boschmann, Alexander ID - 10629 TI - EMG-basierte Ganganalyse ER - TY - GEN AU - Breitlauch, Daniel ID - 10642 TI - Evolvable Cache Controller ER - TY - GEN AU - Dridger, Denis ID - 10649 TI - Soft Microprocessors with tightly coupled Application-Specific Coprocessors ER - TY - GEN AU - Graf, Tobias ID - 10657 TI - Parallelization of the UCT Algorithm on HPC-Clusters ER - TY - CONF AU - Kaufmann, Paul AU - Englehart, Kevin AU - Platzner, Marco ID - 10683 T2 - International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) TI - Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms ER - TY - CONF AU - Kaufmann, Paul AU - Knieper, Tobias AU - Platzner, Marco ID - 10686 T2 - IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) TI - A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers ER - TY - JOUR AU - Kebschull, Udo AU - Platzner, Marco AU - Teich, Jürgen ID - 10694 IS - 3 JF - IET Computers Digital Techniques SN - 1751-8601 TI - Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial) VL - 4 ER - TY - GEN AU - Knieper, Tobias ID - 10697 TI - Hybridization of Global Multi-Objective and Local Search Techniques ER - TY - CONF AU - Knieper, Tobias AU - Kaufmann, Paul AU - Glette, Kyrre AU - Platzner, Marco AU - Torresen, Jim ID - 10699 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture VL - 6274 ER - TY - CHAP AU - Lübbers, Enno AU - Platzner, Marco ED - Platzner, Marco ED - Teich, Jürgen ED - Wehn, Norbert ID - 10704 T2 - Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications TI - ReconOS: An Operating System for Dynamically Reconfigurable Hardware ER - TY - GEN AU - Meiche, Robert ID - 10710 TI - FPGA/CPU Multicore-Plattform für ReconOS/eCos ER - TY - GEN AU - Niekamp, Manuel ID - 10717 TI - Transparente Hardwarebeschleunigung durch Shared Library Interposing ER - TY - GEN AU - Runde, Bodo ID - 10731 TI - A Token-Ring Network-On-Chip for Message Passing in ReconOS ER - TY - GEN AU - Wiersema, Tobias ID - 10752 TI - Scheduling Support for Heterogeneous Hardware Accelerators under Linux ER - TY - BOOK ED - Platzner, Marco ED - Teich, Jürgen ED - Wehn, Norbert ID - 10763 SN - 9048134846 TI - Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications ER - TY - CONF AU - Khatir, Mehrdad AU - Ghasemzadeh Mohammadi, Hassan AU - Ejlali, Alireza ID - 10776 T2 - Computer Design (ICCD), 2010 IEEE International Conference on TI - Sub-threshold charge recovery circuits ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13640 T2 - Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL) TI - A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier ER - TY - CONF AU - Schäfer, Wilhelm AU - Birattari, Mauro AU - Blömer, Johannes AU - Dorigo, Marco AU - Engels, Gregor AU - O'Grady, Rehan AU - Platzner, Marco AU - Rammig, Franz-Josef AU - Reif, Wolfgang AU - Trächtler, Ansgar ID - 13641 T2 - Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER) TI - Engineering Self-Coordinating Software Intensive Systems ER -