TY - CHAP AU - Plessl, Christian AU - Platzner, Marco ED - Khalgui, Mohamed ED - Hanisch, Hans-Michael ID - 2202 SN - 978-1-60960-086-0 T2 - Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility TI - Hardware Virtualization on Dynamically Reconfigurable Embedded Processors ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AB - Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach. AU - Drzevitzky, Stephanie AU - Platzner, Marco ID - 666 T2 - Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco ID - 10637 T2 - Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT) TI - Accurate gait phase detection using surface electromyographic signals and support vector machines ER - TY - CONF AU - Boschmann, Alexander AU - Platzner, Marco AU - Robrecht, Michael AU - Hahn, Martin AU - Winkler, Michael ID - 10638 T2 - Proc. MyoElectric Controls Symposium (MEC) TI - Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems ER - TY - GEN AU - Ikonomakis, Nikolaos ID - 10678 TI - PinSim: Schnelle Simulation mit Pintools ER - TY - GEN AU - Kassner, Hendrik ID - 10680 TI - MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern ER - TY - CHAP AU - Kaufmann, Paul AU - Platzner, Marco ED - Müller-Schloer, Christian ED - Schmeck, Hartmut ED - Ungerer, Theo ID - 10687 T2 - Organic Computing---A Paradigm Shift for Complex Systems TI - Multi-objective Intrinsic Evolution of Embedded Systems VL - 1 ER - TY - GEN AU - Schwabe, Arne ID - 10736 TI - Analysis of Algorithmic Approaches for Temporal Partitioning ER - TY - CHAP AU - Sekanina, Lukas AU - Walker, James Alfred AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 10737 T2 - Cartesian Genetic Programming TI - Evolution of Electronic Circuits ER - TY - CHAP AU - Walker, James Alfred AU - Miller, Julian F. AU - Kaufmann, Paul AU - Platzner, Marco ID - 10748 T2 - Cartesian Genetic Programming TI - Problem Decomposition in Cartesian Genetic Programming ER - TY - GEN AU - Welp, Daniel ID - 10750 TI - User Space Scheduling for Heterogeneous Systems ER - TY - CONF AU - Agne, Andreas AU - Platzner, Marco AU - Lübbers, Enno ID - 13643 SN - 9781457714849 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Memory Virtualization for Multithreaded Reconfigurable Hardware ER - TY - CONF AU - Henkel, Jörg AU - Hedrich, Lars AU - Herkersdorf, Andreas AU - Kapitza, Rüdiger AU - Lohmann, Daniel AU - Marwedel, Peter AU - Platzner, Marco AU - Rosenstiel, Wolfgang AU - Schlichtmann, Ulf AU - Spinczyk, Olaf AU - Tahoori, Mehdi AU - Bauer, Lars AU - Teich, Jürgen AU - Wehn, Norbert AU - Wunderlich, Hans-Joachim AU - Becker, Joachim AU - Bringmann, Oliver AU - Brinkschulte, Uwe AU - Chakraborty, Samarjit AU - Engel, Michael AU - Ernst, Rolf AU - Härtig, Hermann ID - 13644 SN - 9781450307154 T2 - Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11 TI - Design and architectures for dependable embedded systems ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - JOUR AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2201 JF - Int. Journal of Recon- figurable Computing (IJRC) KW - funding-altera TI - FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - JOUR AU - Drzevitzky, Stephanie AU - Kastens, Uwe AU - Platzner, Marco ID - 10605 JF - International Journal of Reconfigurable Computing TI - Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification VL - 2010 ER - TY - GEN AU - Agne, Andreas ID - 10614 TI - Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen ER - TY - GEN AU - Boschmann, Alexander ID - 10629 TI - EMG-basierte Ganganalyse ER - TY - GEN AU - Breitlauch, Daniel ID - 10642 TI - Evolvable Cache Controller ER - TY - GEN AU - Dridger, Denis ID - 10649 TI - Soft Microprocessors with tightly coupled Application-Specific Coprocessors ER - TY - GEN AU - Graf, Tobias ID - 10657 TI - Parallelization of the UCT Algorithm on HPC-Clusters ER - TY - CONF AU - Kaufmann, Paul AU - Englehart, Kevin AU - Platzner, Marco ID - 10683 T2 - International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) TI - Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms ER - TY - CONF AU - Kaufmann, Paul AU - Knieper, Tobias AU - Platzner, Marco ID - 10686 T2 - IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) TI - A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers ER - TY - JOUR AU - Kebschull, Udo AU - Platzner, Marco AU - Teich, Jürgen ID - 10694 IS - 3 JF - IET Computers Digital Techniques SN - 1751-8601 TI - Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial) VL - 4 ER - TY - GEN AU - Knieper, Tobias ID - 10697 TI - Hybridization of Global Multi-Objective and Local Search Techniques ER - TY - CONF AU - Knieper, Tobias AU - Kaufmann, Paul AU - Glette, Kyrre AU - Platzner, Marco AU - Torresen, Jim ID - 10699 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture VL - 6274 ER - TY - CHAP AU - Lübbers, Enno AU - Platzner, Marco ED - Platzner, Marco ED - Teich, Jürgen ED - Wehn, Norbert ID - 10704 T2 - Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications TI - ReconOS: An Operating System for Dynamically Reconfigurable Hardware ER - TY - GEN AU - Meiche, Robert ID - 10710 TI - FPGA/CPU Multicore-Plattform für ReconOS/eCos ER - TY - GEN AU - Niekamp, Manuel ID - 10717 TI - Transparente Hardwarebeschleunigung durch Shared Library Interposing ER - TY - GEN AU - Runde, Bodo ID - 10731 TI - A Token-Ring Network-On-Chip for Message Passing in ReconOS ER - TY - GEN AU - Wiersema, Tobias ID - 10752 TI - Scheduling Support for Heterogeneous Hardware Accelerators under Linux ER - TY - BOOK ED - Platzner, Marco ED - Teich, Jürgen ED - Wehn, Norbert ID - 10763 SN - 9048134846 TI - Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications ER - TY - CONF AU - Khatir, Mehrdad AU - Ghasemzadeh Mohammadi, Hassan AU - Ejlali, Alireza ID - 10776 T2 - Computer Design (ICCD), 2010 IEEE International Conference on TI - Sub-threshold charge recovery circuits ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13640 T2 - Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL) TI - A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier ER - TY - CONF AU - Schäfer, Wilhelm AU - Birattari, Mauro AU - Blömer, Johannes AU - Dorigo, Marco AU - Engels, Gregor AU - O'Grady, Rehan AU - Platzner, Marco AU - Rammig, Franz-Josef AU - Reif, Wolfgang AU - Trächtler, Ansgar ID - 13641 T2 - Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER) TI - Engineering Self-Coordinating Software Intensive Systems ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13642 T2 - Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian AU - Keller, Ariane AU - Plattner, Bernhard ID - 2223 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - GEN ED - Plaks, Toomas P. ED - Andrews, David ED - DeMara, Ronald ED - Lam, Herman ED - Lee, Jooheung ED - Plessl, Christian ED - Stitt, Greg ID - 2222 SN - 1-60132-140-6 TI - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) ER - TY - CONF AU - Beisel, Tobias AU - Niekamp, Manuel AU - Plessl, Christian ID - 2226 SN - 978-1-4244-6965-9 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Boschmann, Alexander AU - Kaufmann, Paul AU - Platzner, Marco AU - Winkler, Michael ID - 10639 T2 - Proc. Technically Assisted Rehabilitation (TAR) TI - Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets ER -