TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13637 T2 - Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) TI - Program-driven Fine-grained Power Management for the Reconfigurable Mesh ER - TY - CONF AU - Happe, Markus AU - Lübbers, Enno AU - Platzner, Marco ID - 13638 SN - 9781424443758 T2 - Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT) TI - An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning ER - TY - CONF AU - Drzevitzky, Stephanie AU - Kastens, Uwe AU - Platzner, Marco ID - 13639 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules ER - TY - CONF AB - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2350 KW - IMORC KW - interconnect KW - performance SN - 978-1-4244-4450-2 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing ER - TY - CONF AB - In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 2262 KW - EvoCache KW - evolvable hardware KW - computer architecture T2 - Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) TI - EvoCaches: Application-specific Adaptation of Cache Mapping ER - TY - CONF AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2238 KW - IMORC KW - graphics SN - 978-0-7695-3917-1 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2261 KW - IMORC KW - NOC KW - KNN KW - accelerator SN - 1946-1488 T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure ER - TY - CONF AB - In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. AU - Grad, Mariusz AU - Plessl, Christian ID - 2263 SN - 1-60132-101-5 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX ER - TY - CONF AU - Beisel, Tobias AU - Lietsch, Stefan AU - Thielemans, Kris ID - 2358 T2 - IEEE Nuclear Science Symposium Conference Record (NSS) TI - A method for OSEM PET reconstruction on parallel architectures using STIR ER - TY - CONF AU - Platzner, Marco AU - Döhre, Sven AU - Happe, Markus AU - Kenter, Tobias AU - Lorenz, Ulf AU - Schumacher, Tobias AU - Send, Andre AU - Warkentin, Alexander ID - 2365 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - The GOmputer: Accelerating GO with FPGAs ER - TY - GEN AU - Boschmann, Alexander ID - 10628 TI - Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen ER - TY - GEN AU - Breitlauch, Daniel ID - 10641 TI - Selbstoptimierender Cache-Kontroller ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10644 TI - Verteilte Simulation von mobilen Robotern mit EyeSim ER - TY - CONF AU - Glette, Kyrre AU - Gruber, Thiemo AU - Kaufmann, Paul AU - Torresen, Jim AU - Sick, Bernhard AU - Platzner, Marco ID - 10653 T2 - IEEE Adaptive Hardware and Systems (AHS) TI - Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control ER - TY - CONF AU - Glette, Kyrre AU - Torresen, Jim AU - Kaufmann, Paul AU - Platzner, Marco ID - 10656 T2 - IEEE Intl. Conf. on Evolvable Systems (ICES) TI - A Comparison of Evolvable Hardware Architectures for Classification Tasks VL - 5216 ER - TY - GEN AU - Happe, Markus ID - 10669 TI - Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern ER - TY - GEN AU - Torresen, Jim AU - Glette, Kyrre AU - Platzner, Marco AU - Kaufmann, Paul ID - 10690 TI - Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS) ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10691 T2 - Genetic and Evolutionary Computation (GECCO) TI - Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming ER - TY - GEN AU - Knieper, Tobias ID - 10696 TI - Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf ER - TY - CONF AU - Knieper, Tobias AU - Defo, Bertrand AU - Kaufmann, Paul AU - Platzner, Marco ID - 10698 T2 - Biologically Inspired Collaborative Computing (BICC) TI - On Robust Evolution of Digital Hardware VL - 268 ER - TY - GEN AU - Niklas, Jörg ID - 10718 TI - Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme ER - TY - GEN AU - Östermann, Marco ID - 10721 TI - Raytracing on a Custom Instruction Set CPU ER - TY - GEN AU - Westerheide, Nico ID - 10751 TI - Design and Evaluation of MicroBlaze Multi-core Architectures ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Tabkhi, Hamed AU - Miremadi, Seyed Ghassem AU - Ejlali, Alireza ID - 10778 T2 - 2008 International Conference on Microelectronics TI - A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13629 T2 - Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS) TI - Realizing Reconfigurable Mesh Algorithms on Softcore Arrays ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13630 T2 - Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Communication and Synchronization in Multithreaded Reconfigurable Computing Systems ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13631 SN - 9781424419609 T2 - Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL) TI - A portable abstraction layer for hardware threads ER - TY - CONF AU - Schumacher, Tobias AU - Meiche, Robert AU - Kaufmann, Paul AU - Lübbers, Enno AU - Plessl, Christian AU - Platzner, Marco ID - 2364 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Hardware Accelerator for k-th Nearest Neighbor Thinning ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2372 KW - IMORC KW - IP core KW - interconnect T2 - Many-core and Reconfigurable Supercomputing Conference (MRSC) TI - IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers ER - TY - CONF AB - In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits. AU - Kaufmann, Paul AU - Platzner, Marco ID - 6508 KW - integrated circuit design KW - hardware evolution KW - evolutionary hardware design KW - evolutionary optimizers KW - hash functions KW - preengineered circuits KW - Hardware KW - Circuits KW - Design optimization KW - Visualization KW - Genetic programming KW - Genetic mutations KW - Clustering algorithms KW - Biological cells KW - Field programmable gate arrays KW - Routing SN - 076952866X T2 - Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) TI - MOVES: A Modular Framework for Hardware Evolution ER - TY - GEN AU - Beisel, Tobias ID - 10623 TI - Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen ER - TY - JOUR AU - Bergmann, Neil AU - Platzner, Marco AU - Teich, Jürgen ID - 10625 JF - {EURASIP} Journal on Embedded Systems TI - Dynamically Reconfigurable Architectures (editorial) VL - 2007 ER - TY - GEN AU - Ceylan, Toni AU - Yalcin, Coni ID - 10643 TI - Distributed Simulation of mobile Robots using EyeSim ER - TY - JOUR AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 10646 IS - 4 JF - IET Computers Digital Techniques KW - reconfigurable architectures KW - resource allocation KW - device reconfiguration time KW - dynamic hardware reconfiguration KW - dynamically reconfigurable hardware KW - light-weight runtime system KW - merge server distribute load KW - periodic real-time tasks KW - runtime system overheads KW - schedulability analysis KW - scheduling technique KW - server-based execution KW - synthesis tool flow SN - 1751-8601 TI - Server-based execution of periodic tasks on dynamically reconfigurable hardware VL - 1 ER - TY - GEN AU - Defo, Bertrand ID - 10647 TI - A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization ER - TY - GEN AU - Döhre, Sven ID - 10648 TI - Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10689 T2 - Architecture of Computing Systems (ARCS) TI - Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution VL - 4415 ER - TY - GEN AU - Meiche, Robert ID - 10709 TI - VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen ER - TY - GEN AU - Reisch, Waldemar ID - 10728 TI - Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS ER - TY - GEN AU - Rethmeier, Eike ID - 10729 TI - Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem ER - TY - CONF AU - Schumacher, Tobias AU - Lübbers, Enno AU - Kaufmann, Paul AU - Platzner, Marco ID - 10735 T2 - Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) TI - Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster VL - 15 ER - TY - CONF AU - Giefers, Heiner AU - Platzner, Marco ID - 13627 SN - 9781424410590 T2 - Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) TI - A Many-Core Implementation Based on the Reconfigurable Mesh Model ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco ID - 13628 SN - 9781424410590 T2 - Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) TI - ReconOS: An RTOS Supporting Hard-and Software Threads ER - TY - CONF AB - This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. AU - Plessl, Christian AU - Platzner, Marco AU - Thiele, Lothar ID - 2401 KW - temporal partitioning KW - retiming KW - ILP T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - Optimal Temporal Partitioning based on Slowdown and Retiming ER - TY - CONF AU - Kaufmann, Paul AU - Platzner, Marco ID - 10688 T2 - Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD) TI - Multi-objective Intrinsic Hardware Evolution ER - TY - GEN AU - Mühlenbernd, Roland ID - 10716 TI - FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks ER - TY - CONF AU - Danne, Klaus AU - Mühlenbernd, Roland AU - Platzner, Marco ID - 13624 T2 - Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) TI - Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13625 T2 - In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) TI - An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13626 T2 - Proceedings of the 13th Reconfigurable Architectures Workshop (RAW) TI - Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware ER - TY - CONF AB - This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. AU - Plessl, Christian AU - Platzner, Marco ID - 2411 KW - Zippy T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Zippy – A coarse-grained reconfigurable array with support for hardware virtualization ER -