Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf - Knieper, Tobias

On Robust Evolution of Digital Hardware - Knieper, Tobias; Defo, Bertrand; Kaufmann, Paul; Platzner, Marco (Biologically Inspired Collaborative Computing (BICC))

Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme - Niklas, Jörg

Raytracing on a Custom Instruction Set CPU - Östermann, Marco

Design and Evaluation of MicroBlaze Multi-core Architectures - Westerheide, Nico

A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic - Ghasemzadeh Mohammadi, Hassan; Tabkhi, Hamed; Miremadi, Seyed Ghassem; Ejlali, Alireza (2008 International Conference on Microelectronics)

Realizing Reconfigurable Mesh Algorithms on Softcore Arrays - Giefers, Heiner; Platzner, Marco (Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS))

Communication and Synchronization in Multithreaded Reconfigurable Computing Systems - Lübbers, Enno; Platzner, Marco (Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA))

A portable abstraction layer for hardware threads - Lübbers, Enno; Platzner, Marco (Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL))

A Hardware Accelerator for k-th Nearest Neighbor Thinning - Schumacher, Tobias; Meiche, Robert; Kaufmann, Paul; Lübbers, Enno; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))

IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers - Schumacher, Tobias; Plessl, Christian; Platzner, Marco (Many-core and Reconfigurable Supercomputing Conference (MRSC))
Keywords: IMORC; IP core; interconnect

MOVES: A Modular Framework for Hardware Evolution - Kaufmann, Paul; Platzner, Marco (Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007))
In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.
Keywords: integrated circuit design; hardware evolution; evolutionary hardware design; evolutionary optimizers; hash functions; preengineered circuits; Hardware; Circuits; Design optimization; Visualization; Genetic programming; Genetic mutations; Clustering algorithms; Biological cells; Field programmable gate arrays; Routing

Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen - Beisel, Tobias

Dynamically Reconfigurable Architectures (editorial) - Bergmann, Neil; Platzner, Marco; Teich, Jürgen (EURASIP Journal on Embedded Systems)

Distributed Simulation of mobile Robots using EyeSim - Ceylan, Toni; Yalcin, Coni

Server-based execution of periodic tasks on dynamically reconfigurable hardware - Danne, Klaus; Mühlenbernd, Roland; Platzner, Marco (IET Computers Digital Techniques)
Keywords: reconfigurable architectures; resource allocation; device reconfiguration time; dynamic hardware reconfiguration; dynamically reconfigurable hardware; light-weight runtime system; merge server distribute load; periodic real-time tasks; runtime system overheads; schedulability analysis; scheduling technique; server-based execution; synthesis tool flow

A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization - Defo, Bertrand

Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme - Döhre, Sven

Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution - Kaufmann, Paul; Platzner, Marco (Architecture of Computing Systems (ARCS))

VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen - Meiche, Robert

Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS - Reisch, Waldemar

Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem - Rethmeier, Eike

Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster - Schumacher, Tobias; Lübbers, Enno; Kaufmann, Paul; Platzner, Marco (Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO))

A Many-Core Implementation Based on the Reconfigurable Mesh Model - Giefers, Heiner; Platzner, Marco (Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL))

ReconOS: An RTOS Supporting Hard-and Software Threads - Lübbers, Enno; Platzner, Marco (Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL))

Optimal Temporal Partitioning based on Slowdown and Retiming - Plessl, Christian; Platzner, Marco; Thiele, Lothar (Proc. Int. Conf. on Field Programmable Technology (ICFPT))
This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture.
Keywords: temporal partitioning; retiming; ILP

Multi-objective Intrinsic Hardware Evolution - Kaufmann, Paul; Platzner, Marco (Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD))

FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks - Mühlenbernd, Roland

Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions - Danne, Klaus; Mühlenbernd, Roland; Platzner, Marco (Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL))

An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices - Danne, Klaus; Platzner, Marco (In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES))

Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware - Danne, Klaus; Platzner, Marco (Proceedings of the 13th Reconfigurable Architectures Workshop (RAW))

Zippy – A coarse-grained reconfigurable array with support for hardware virtualization - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP))
This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder.
Keywords: Zippy

System-level performance evaluation of reconfigurable processors - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Microprocessors and Microsystems)
Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.
Keywords: FPGA; reconfigurable computing; co-simulation; Zippy

Periodic real-time scheduling for FPGA computers - Danne, Klaus; Platzner, Marco (Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES))

Memory-demanding Periodic Real-time Applications on FPGA Computers - Danne, Klaus; Platzner, Marco (Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS))

A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware - Danne, Klaus; Platzner, Marco (Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL))

Virtualization of Hardware – Introduction and Survey - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field.
Keywords: hardware virtualization

Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks - Steiger, Christoph; Walder, Herbert; Platzner, Marco (IEEE Transactions on Computers)

A Runtime Environment for Reconfigurable Hardware Operating Systems - Walder, Herbert; Platzner, Marco (Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL))

XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems - Walder, Hebert; Nobs, Samuel; Platzner, Marco (Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine - Dyer, Matthias; Platzner, Marco; Thiele, Lothar (Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM))

TKDM – A Reconfigurable Co-processor in a PC's Memory Slot - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Technology (ICFPT))
This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces.
Keywords: coprocessor; DIMM; memory bus; FPGA; high performance computing

The Case for Reconfigurable Hardware in Wearable Computing - Plessl, Christian; Enzler, Rolf; Walder, Herbert; Beutel, Jan; Platzner, Marco; Thiele, Lothar; Tröster, Gerhard (Personal and Ubiquitous Computing)
Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.

Instance-Specific Accelerators for Minimum Covering - Plessl, Christian; Platzner, Marco (Journal of Supercomputing)
This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch & bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch & bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups.
Keywords: reconfigurable computing; instance-specific acceleration; minimum covering

Virtualizing Hardware with Multi-Context Reconfigurable Arrays - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.
Keywords: Zippy; multi-context; FPGA

Co-simulation of a Hybrid Multi-Context Architecture - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.
Keywords: Zippy; co-simulation

Online scheduling for block-partitioned reconfigurable devices - Walder, Herbert; Platzner, Marco (Proceedings Design, Automation and Test in Europe Conference (DATE))

Fast online task placement on FPGAs: free space partitioning and 2D-hashing - Walder, Herbert; Steiger, Christoph; Platzner, Marco (Proceedings International Parallel and Distributed Processing Symposium)

Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations - Walder, Herbert; Platzner, Marco (Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices - Steiger, Christoph; Walder, Herbert; Platzner, Marco (Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL))