TY - JOUR AB - Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2412 IS - 2-3 JF - Microprocessors and Microsystems KW - FPGA KW - reconfigurable computing KW - co-simulation KW - Zippy TI - System-level performance evaluation of reconfigurable processors VL - 29 ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13621 SN - 3902463031 T2 - Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES) TI - Periodic real-time scheduling for FPGA computers ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13622 T2 - Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS) TI - Memory-demanding Periodic Real-time Applications on FPGA Computers ER - TY - CONF AU - Danne, Klaus AU - Platzner, Marco ID - 13623 SN - 0780393627 T2 - Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL) TI - A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware ER - TY - CONF AB - In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. AU - Plessl, Christian AU - Platzner, Marco ID - 2415 KW - hardware virtualization T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Virtualization of Hardware – Introduction and Survey ER - TY - JOUR AU - Steiger, Christoph AU - Walder, Herbert AU - Platzner, Marco ID - 10742 IS - 11 JF - {IEEE} Transactions on Computers TI - Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks VL - 53 ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13618 SN - 0302-9743 T2 - Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) TI - A Runtime Environment for Reconfigurable Hardware Operating Systems ER - TY - CONF AU - Walder, Hebert AU - Nobs, Samuel AU - Platzner, Marco ID - 13619 T2 - Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems ER - TY - CONF AU - Dyer, Matthias AU - Platzner, Marco AU - Thiele, Lothar ID - 13620 SN - 0769522300 T2 - Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) TI - Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine ER - TY - CONF AB - This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. AU - Plessl, Christian AU - Platzner, Marco ID - 2418 KW - coprocessor KW - DIMM KW - memory bus KW - FPGA KW - high performance computing T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - TKDM – A Reconfigurable Co-processor in a PC's Memory Slot ER - TY - JOUR AB - Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM. AU - Plessl, Christian AU - Enzler, Rolf AU - Walder, Herbert AU - Beutel, Jan AU - Platzner, Marco AU - Thiele, Lothar AU - Tröster, Gerhard ID - 2419 IS - 5 JF - Personal and Ubiquitous Computing TI - The Case for Reconfigurable Hardware in Wearable Computing VL - 7 ER - TY - JOUR AB - This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. AU - Plessl, Christian AU - Platzner, Marco ID - 2420 IS - 2 JF - Journal of Supercomputing KW - reconfigurable computing KW - instance-specific acceleration KW - minimum covering SN - 0920-8542 TI - Instance-Specific Accelerators for Minimum Covering VL - 26 ER - TY - CONF AB - In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2421 KW - Zippy KW - multi-context KW - FPGA T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Virtualizing Hardware with Multi-Context Reconfigurable Arrays VL - 2778 ER - TY - CONF AB - Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2422 KW - Zippy KW - co-simulation SN - 1-932415-05-X T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Co-simulation of a Hybrid Multi-Context Architecture ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13612 SN - 0769518702 T2 - Proceedings Design, Automation and Test in Europe Conference (DATE) TI - Online scheduling for block-partitioned reconfigurable devices ER - TY - CONF AU - Walder, Herbert AU - Steiger, Christoph AU - Platzner, Marco ID - 13613 SN - 0769519261 T2 - Proceedings International Parallel and Distributed Processing Symposium TI - Fast online task placement on FPGAs: free space partitioning and 2D-hashing ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13614 T2 - Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations ER - TY - CONF AU - Steiger, Christoph AU - Walder, Herbert AU - Platzner, Marco ID - 13615 SN - 0302-9743 T2 - Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) TI - Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices ER - TY - CONF AU - Steiger, Christoph AU - Walder, Herbert AU - Platzner, Marco AU - Thiele, Lothar ID - 13617 SN - 0769520448 T2 - Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) TI - Online scheduling and placement of real-time tasks to partially reconfigurable devices ER - TY - CONF AB - Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM. AU - Plessl, Christian AU - Enzler, Rolf AU - Walder, Herbert AU - Beutel, Jan AU - Platzner, Marco AU - Thiele, Lothar ID - 2423 KW - wearable computing SN - 0-7695-1816-8 T2 - Proc. Int. Symp. on Wearable Computers (ISWC) TI - Reconfigurable Hardware in Wearable Computing Nodes ER - TY - CONF AB - Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. AU - Dyer, Matthias AU - Plessl, Christian AU - Platzner, Marco ID - 2424 KW - partial reconfiguration T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Partially Reconfigurable Cores for Xilinx Virtex VL - 2438 ER - TY - CONF AB - We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. AU - Plessl, Christian AU - Platzner, Marco ID - 2425 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - Custom Computing Machines for the Set Covering Problem ER - TY - JOUR AU - Eisenring, Michael AU - Platzner, Marco ID - 10651 IS - 2 JF - The Journal of Supercomputing TI - A Framework for Run-time Reconfigurable Systems VL - 21 ER - TY - CONF AU - Walder, Herbert AU - Platzner, Marco ID - 13611 T2 - Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform ER - TY - CONF AB - In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. AU - Plessl, Christian AU - Platzner, Marco ID - 2428 KW - minimum covering KW - accelerator KW - funding-sundance T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Instance-Specific Accelerators for Minimum Covering ER - TY - CONF AB - In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core. AU - Enzler, Rolf AU - Platzner, Marco AU - Plessl, Christian AU - Thiele, Lothar AU - Tröster, Gerhard ID - 2432 KW - benchmark T2 - Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III TI - Reconfigurable Processors for Handhelds and Wearables: Application Analysis VL - 4525 ER - TY - JOUR AU - Mencer, Oskar AU - Platzner, Marco AU - Morf, Martin AU - J. Flynn, Michael ID - 10713 IS - 1 JF - {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems TI - Object-oriented domain specific compilers for programming FPGAs VL - 9 ER - TY - GEN AU - Enzler, Rolf AU - Platzner, Marco ID - 13463 TI - Dynamically Reconfigurable Processors ER - TY - JOUR AU - Platzner, Marco ID - 6507 IS - 4 JF - Computer SN - 0018-9162 TI - Reconfigurable accelerators for combinatorial problems VL - 33 ER - TY - JOUR AU - Eisenring, Michael AU - Platzner, Marco ID - 10606 JF - IEE Proceedings -- Computers & Digital Techniques TI - Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems VL - 147 ER - TY - JOUR AU - Platzner, Marco AU - Rinner, Bernhard AU - Weiss, Reinhold ID - 10725 IS - 2 JF - IEEE Intelligent Systems TI - Toward embedded qualitative simulation: a specialized computer architecture for QSim VL - 15 ER - TY - CONF AU - Eisenring, Michael H. AU - Platzner, Marco ID - 13609 T2 - Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) TI - An Implementation Framework for Run-time Reconfigurable Systems ER - TY - CONF AU - Eisenring, Michael AU - Platzner, Marco ID - 13610 T2 - Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) TI - Optimization of Run-time Reconfigurable Embedded Systems ER - TY - CONF AU - Mencer, Oskar AU - Platzner, Marco ID - 13607 SN - 0769500013 T2 - Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32) TI - Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment ER - TY - CONF AU - Eisenring, Michael AU - Platzner, Marco AU - Thiele, Lothar ID - 13608 SN - 0302-9743 T2 - Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) TI - Communication Synthesis for Reconfigurable Embedded Systems VL - 1673 ER - TY - JOUR AU - Platzner, Marco ID - 10607 JF - e&i Elektrotechnik und Informationstechnik TI - Reconfigurable Computer Architectures VL - 115 ER - TY - JOUR AU - Platzner, Marco AU - Rinner, Bernhard ID - 10608 JF - International Journal of Computers & Their Applications TI - Design and Implementation of a Parallel Constraint Satisfaction Algorithm VL - 5 ER - TY - GEN AU - Platzner, Marco AU - Rinner, Bernhard AU - Weiss, Reinhold ID - 13464 TI - A Distributed Computer Architecture for Fast Qualitative Simulation ER - TY - CONF AU - Platzner, Marco AU - De Micheli, Giovanni ID - 13606 SN - 0302-9743 T2 - Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) TI - Acceleration of satisfiability algorithms by reconfigurable hardware ER - TY - JOUR AU - Platzner, Marco AU - Rinner, Bernhard AU - Weiss, Reinhold ID - 10609 JF - e & i Elektrotechnik und Informationstechnik TI - A Computer Architecture to Support Qualitative Simulation in Industrial Applications VL - 114 ER - TY - JOUR AU - Platzner, Marco AU - Rinner, Bernhard AU - Weiss, Reinhold ID - 10724 IS - 7-8 JF - Simulation Practice and Theory TI - Parallel qualitative simulation VL - 5 ER - TY - CONF AU - Platzner, Marco AU - Peters, Liliane ID - 13603 T2 - Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing TI - Fast Signature Segmentation on a Multi-DSP Architecture VL - 3166 ER - TY - CONF AU - Röwekamp, Thomas AU - Platzner, Marco AU - Peters, Liliane ID - 13604 T2 - Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT) TI - Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP ER - TY - CONF AU - Lind, Erich AU - Platzner, Marco AU - Rinner, Bernhard ID - 13602 T2 - Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT) TI - A Multi-DSP System with Dynamically Reconfigurable Processors ER - TY - JOUR AU - Platzner, Marco AU - Rinner, Bernhard AU - Weiss, Reinhold ID - 10610 JF - J.UCS Journal of Universal Computer Science TI - Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation VL - 12 ER - TY - CONF AU - Platzner, Marco AU - Rinner, Bernhard AU - Weiss, Reinhold ID - 13469 T2 - Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing TI - A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs ER - TY - CONF AU - Brenner, Eugen AU - Ginthör-Kalcsics, Robert AU - Hranitzky, Robert AU - Platzner, Marco AU - Rinner, Bernhard AU - Steger, Christian AU - Weiss, Reinhold ID - 13470 T2 - Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference TI - High-Performance Simulators Based on Multi-TMS320C40 ER - TY - CONF AU - Friedl, Gerald AU - Platzner, Marco AU - Rinner, Bernhard ID - 13471 T2 - Proceedings of the EURO-PAR'95 International Conference on Parallel Processing TI - A Special-Purpose Coprocessor for Qualitative Simulation ER - TY - CONF AU - Platzner, Marco AU - Rinner, Bernhard AU - Weiss, Reinhold ID - 13472 T2 - Proceedings of the EUROSIM Congress TI - Parallel Qualitative Simulation ER - TY - CONF AU - Platzner, Marco AU - Rinner, Bernhard ID - 13473 T2 - Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems TI - Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture ER -