TY - GEN AB - Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis. AU - Keerthipati, Monica ID - 15920 TI - A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking ER - TY - GEN AU - Sabu, Nithin S. ID - 14831 TI - FPGA Acceleration of String Search Techniques in Huge Data Sets ER - TY - GEN AU - Mehta, Jinay ID - 15946 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip ER - TY - GEN AU - Hansmeier, Tim ID - 14546 TI - Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers ER - TY - CONF AU - Guettatfi, Zakarya AU - Platzner, Marco AU - Kermia, Omar AU - Khouas, Abdelhakim ID - 31067 T2 - 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) TI - An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware ER - TY - CONF AB - Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers. AU - Ahmed, Qazi Arbab AU - Wiersema, Tobias AU - Platzner, Marco ED - Hochberger, Christian ED - Nelson, Brent ED - Koch, Andreas ED - Woods, Roger ED - Diniz, Pedro ID - 9913 SN - 978-3-030-17227-5 T2 - Applied Reconfigurable Computing TI - Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan VL - 11444 ER - TY - GEN AU - Lienen, Christian ID - 15874 TI - Implementing a Real-time System on a Platform FPGA operated with ReconOS ER - TY - JOUR AU - Platzner, Marco AU - Plessl, Christian ID - 12871 JF - Informatik Spektrum SN - 0170-6012 TI - FPGAs im Rechenzentrum ER - TY - GEN AU - Mehta, Jinay D ID - 52478 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip ER - TY - CONF AB - Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node. AU - Lösch, Achim AU - Wiens, Alex AU - Platzner, Marco ID - 3362 SN - 0302-9743 T2 - Proceedings of the International Conference on Architecture of Computing Systems (ARCS) TI - Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes VL - 10793 ER - TY - GEN AU - Schnuer, Jan-Philip ID - 3365 TI - Static Scheduling Algorithms for Heterogeneous Compute Nodes ER - TY - GEN AU - Croce, Marcel ID - 3366 TI - Evaluation of OpenCL-based Compilation for FPGAs ER - TY - CONF AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Andrews, David ID - 3373 SN - 0302-9743 T2 - ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications TI - An FPGA/HMC-Based Accelerator for Resolution Proof Checking VL - 10824 ER - TY - GEN AB - Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Ghasemzadeh Mohammadi, Hassan AU - Awais, Muhammad AU - Platzner, Marco ID - 3586 KW - Approximate Computing KW - Framework KW - Pareto Front KW - Accuracy T2 - Third Workshop on Approximate Computing (AxC 2018) TI - CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation ER - TY - THES AB - Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches. AU - Ho, Nam ID - 3720 TI - FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization ER - TY - GEN AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 1165 T2 - 4th Workshop On Approximate Computing (WAPCO 2018) TI - Making the Case for Proof-carrying Approximate Circuits ER - TY - CONF AU - Lösch, Achim AU - Platzner, Marco ID - 5547 SN - 9781538674796 T2 - 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes ER - TY - CONF AB - Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 10598 KW - Approximate computing KW - High-level synthesis KW - Accuracy KW - Monte-Carlo tree search KW - Circuit simulation T2 - 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) TI - An MCTS-based Framework for Synthesis of Approximate Circuits ER - TY - GEN AU - Clausing, Lennart ID - 10782 TI - Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data ER - TY - GEN AU - Jentzsch, Felix Paul ID - 1097 KW - Approximate Computing KW - Proof-Carrying Hardware KW - Formal Verification TI - Enforcing IP Core Connection Properties with Verifiable Security Monitors ER - TY - JOUR AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Li, Zhiwu AU - Alnowibet, Khalid AU - Platzner, Marco ID - 12965 JF - IEEE Access SN - 2169-3536 TI - R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints ER - TY - GEN AU - Hansmeier, Tim ID - 3580 TI - An FPGA Accelerator for Checking Resolution Proofs ER - TY - GEN AU - Witschen, Linus Matthias ID - 1157 TI - A Framework for the Synthesis of Approximate Circuits ER - TY - GEN AU - Knorr, Christoph ID - 74 TI - OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten ER - TY - JOUR AB - This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network. AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 9919 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) KW - Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies VL - 94 ER - TY - CONF AB - Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules. AU - Lösch, Achim AU - Platzner, Marco ID - 65 T2 - Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements ER - TY - JOUR AB - Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits. AU - Isenberg, Tobias AU - Platzner, Marco AU - Wehrheim, Heike AU - Wiersema, Tobias ID - 68 IS - 4 JF - ACM Transactions on Design Automation of Electronic Systems TI - Proof-Carrying Hardware via Inductive Invariants ER - TY - JOUR AU - H.W. Leong, Philip AU - Amano, Hideharu AU - Anderson, Jason AU - Bertels, Koen AU - M.P. Cardoso, Jo\~{a}o AU - Diessel, Oliver AU - Gogniat, Guy AU - Hutton, Mike AU - Lee, JunKyu AU - Luk, Wayne AU - Lysaght, Patrick AU - Platzner, Marco AU - K. Prasanna, Viktor AU - Rissa, Tero AU - Silvano, Cristina AU - So, Hayden AU - Wang, Yu ID - 10600 JF - ACM Transactions on Reconfigurable Technology and Systems TI - The First 25 Years of the FPL Conference – Significant Papers ER - TY - JOUR AU - F. DeMara, Ronald AU - Platzner, Marco AU - Ottavi, Marco ID - 10601 JF - IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing TI - Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial) ER - TY - JOUR AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10611 JF - Microprocessors and Microsystems TI - Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus ER - TY - GEN AU - Kaltschmidt, Christian ID - 10613 TI - An AR-based Training and Assessment System for Myoelectrical Prosthetic Control ER - TY - CONF AU - Boschmann, Alexander AU - Thombansen, Georg AU - Witschen, Linus Matthias AU - Wiens, Alex AU - Platzner, Marco ID - 10630 T2 - Design, Automation and Test in Europe (DATE) TI - A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller ER - TY - GEN AU - Riaz, Umair ID - 10666 TI - Acceleration of Industrial Analytics Functions on a Platform FPGA ER - TY - CONF AU - Ho, Nam AU - Ashraf, Ishraq Ibne AU - Kaufmann, Paul AU - Platzner, Marco ID - 10672 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10676 KW - Linux KW - cache storage KW - microprocessor chips KW - multiprocessing systems KW - LEON3-Linux based multicore processor KW - MiBench suite KW - block sizes KW - cache adaptation KW - evolvable caches KW - memory-to-cache-index mapping function KW - processor caches KW - reconfigurable cache mapping optimization KW - reconfigurable hardware technology KW - replacement strategies KW - standard Linux OS KW - time a complete hardware implementation KW - Hardware KW - Indexes KW - Linux KW - Measurement KW - Multicore processing KW - Optimization KW - Training T2 - 2017 International Conference on Field Programmable Technology (ICFPT) TI - Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10692 JF - Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) TI - Three-Stage Power System Restoration Methodology Considering Renewable Energies ER - TY - GEN AU - Dietrich, Andreas ID - 10708 TI - Reconfigurable Cryptographic Services ER - TY - JOUR AU - Shen, Cong AU - Kaufmann, Paul AU - Braun, Martin ID - 10740 JF - The Journal of Engineering TI - Fast Network Restoration by Partitioning of Parallel Black Start Zones ER - TY - BOOK AU - Squillero, Giovanni AU - Burelli, Paolo AU - M. Mora, Antonio AU - Agapitos, Alexandros AU - S. Bush, William AU - Cagnoni, Stefano AU - Cotta, Carlos AU - De Falco, Ivanoe AU - Della Cioppa, Antonio AU - Divina, Federico AU - Eiben, A.E. AU - I. Esparcia-Alc{\'a}zar, Anna AU - Fern{\'a}ndez de Vega, Francisco AU - Glette, Kyrre AU - Haasdijk, Evert AU - Ignacio Hidalgo, J. AU - Kampouridis, Michael AU - Kaufmann, Paul AU - Mavrovouniotis, Michalis AU - Thanh Nguyen, Trung AU - Schaefer, Robert AU - Sim, Kevin AU - Tarantino, Ernesto AU - Urquhart, Neil AU - Zhang (editors), Mengjie ID - 10759 TI - Applications of Evolutionary Computation - 20th European Conference, EvoApplications ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10760 T2 - KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI TI - Parametrizing Cartesian Genetic Programming: An Empirical Study ER - TY - CONF AU - Kaufmann, Paul AU - Ho, Nam AU - Platzner, Marco ID - 10761 T2 - Adaptive Hardware and Systems (AHS) TI - Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10762 T2 - Genetic and Evolutionary Computation (GECCO), Compendium TI - An Empirical Study on the Parametrization of Cartesian Genetic Programming ER - TY - CONF AU - Guettatfi, Zakarya AU - Hübner, Philipp AU - Platzner, Marco AU - Rinner, Bernhard ID - 10780 KW - embedded systems KW - image sensors KW - power aware computing KW - wireless sensor networks KW - Zynq-based VSN node prototype KW - computational self-awareness KW - design approach KW - platform levels KW - power consumption KW - visual sensor networks KW - visual sensor nodes KW - Cameras KW - Hardware KW - Middleware KW - Multicore processing KW - Operating systems KW - Runtime KW - Reconfigurable platforms KW - distributed embedded systems KW - performance-resource trade-off KW - self-awareness KW - visual sensor nodes T2 - 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Computational self-awareness as design approach for visual sensor nodes ER - TY - CONF AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Platzner, Marco ID - 14893 SN - 1865-0929 T2 - Communications in Computer and Information Science TI - I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems ER - TY - JOUR AB - Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved. AU - Wiersema, Tobias AU - Bockhorn, Arne AU - Platzner, Marco ID - 222 JF - Computers & Electrical Engineering TI - An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip ER - TY - CONF AU - Boschmann, Alexander AU - Agne, Andreas AU - Witschen, Linus AU - Thombansen, Georg AU - Kraus, Florian AU - Platzner, Marco ID - 5812 SN - 9781467394062 T2 - 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - FPGA-based acceleration of high density myoelectric signal processing ER - TY - GEN AU - Cedric Mertens, Jan ID - 10612 TI - Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion ER - TY - GEN AU - Nassery, Abdul Sami ID - 10616 TI - Implementation of Bilinear Pairings on Reconfigurable Hardware ER - TY - GEN AU - Amin, Omair ID - 10617 TI - Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method ER - TY - CONF AU - Anwer, Jahanzeb AU - Platzner, Marco ID - 10622 T2 - Euromicro Conference on Digital System Design (DSD) TI - Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs ER -