TY - THES AU - Witschen, Linus Matthias ID - 34041 TI - Frameworks and Methodologies for Search-based Approximate Logic Synthesis ER - TY - CONF AU - Ahmed, Qazi Arbab AU - Platzner, Marco ID - 32342 TI - On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs ER - TY - GEN AU - Mehlich, Florian ID - 42839 TI - An Evaluation of XCS on the OpenAI Gym ER - TY - JOUR AB - Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes. AU - Jentzsch, Felix AU - Umuroglu, Yaman AU - Pappalardo, Alessandro AU - Blott, Michaela AU - Platzner, Marco ID - 33990 IS - 6 JF - IEEE Micro TI - RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures VL - 42 ER - TY - GEN AU - Tcheussi Ngayap, Vanessa Ingrid ID - 45715 TI - FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators ER - TY - GEN AU - Manjunatha, Suraj ID - 45914 TI - Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive Maintenance ER - TY - GEN AU - Kaur , Parvinder ID - 45915 TI - Analysis of Time-Series Classification in Conditional Monitoring Systems ER - TY - THES AB - Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts. This thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques. AU - Wiersema, Tobias ID - 26746 KW - Proof-Carrying Hardware KW - Formal Verification KW - Sequential Circuits KW - Non-Functional Properties KW - Functional Properties TI - Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware ER - TY - JOUR AB - Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach. AU - Lienen, Christian AU - Platzner, Marco ID - 29150 JF - ACM Transactions on Reconfigurable Technology and Systems SN - 1936-7406 TI - Design of Distributed Reconfigurable Robotics Systems with ReconROS ER - TY - GEN AB - Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique. AU - Kashikar, Chinmay ID - 29151 TI - A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes ER - TY - CONF AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 21610 T2 - Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021 TI - LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis ER - TY - GEN AU - Rehnen, Jakob Werner ID - 22216 TI - Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib ER - TY - CONF AB - Approximate computing (AC) has acquired significant maturity in recent years as a promising approach to obtain energy and area-efficient hardware. Automated approximate accelerator synthesis involves a great deal of complexity on the size of design space which exponentially grows with the number of possible approximations. Design space exploration of approximate accelerator synthesis is usually targeted via heuristic-based search methods. The majority of existing frameworks prune a large part of the design space using a greedy-based approach to keep the problem tractable. Therefore, they result in inferior solutions since many potential solutions are neglected in the pruning process without the possibility of backtracking of removed approximate instances. In this paper, we address the aforementioned issue by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based search algorithm, in the context of automated synthesis of approximate accelerators. This enables the synthesis frameworks to deeply subsamples the design space of approximate accelerator synthesis toward most promising approximate instances based on the required performance goals, i.e., power consumption, area, or/and delay. We investigated the challenges of providing an efficient open-source framework that benefits analytical and search-based approximation techniques simultaneously to both speed up the synthesis runtime and improve the quality of obtained results. Besides, we studied the utilization of machine learning algorithms to improve the performance of several critical steps, i.e., accelerator quality testing, in the synthesis framework. The proposed framework can help the community to rapidly generate efficient approximate accelerators in a reasonable runtime. AU - Awais, Muhammad AU - Platzner, Marco ID - 22309 KW - Approximate computing KW - Design space exploration KW - Accelerator synthesis T2 - Proceedings of IEEE Computer Society Annual Symposium on VLSI TI - MCTS-Based Synthesis Towards Efficient Approximate Accelerators ER - TY - GEN AB - This bachelor thesis presents a C/C++ implementation of the XCS algorithm for an embedded system and profiling results concerning the execution time of the functions. These are then analyzed in relation to the input characteristics of the examined learning environments and compared with related work. Three main conclusions can be drawn from the measured results. First, the maximum size of the population of the classifiers influences the runtime of the genetic algorithm; second, the size of the input space has a direct effect on the execution time of the matching function; and last, a larger action space results in a longer runtime generating the prediction for the possible actions. The dependencies identified here can serve to optimize the computational efficiency and make XCS more suitable for embedded systems. AU - Brede, Mathis ID - 22483 TI - Implementation and Profiling of XCS in the Context of Embedded Systems ER - TY - CONF AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Raeisi Nafchi, Masood AU - Bockhorn, Arne AU - Platzner, Marco ED - Hannig, Frank ED - Derrien, Steven ED - Diniz, Pedro ED - Chillet, Daniel ID - 21953 T2 - Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21) TI - Timing Optimization for Virtual FPGA Configurations ER - TY - JOUR AB - Abstract Background Hand amputation can have a truly debilitating impact on the life of the affected person. A multifunctional myoelectric prosthesis controlled using pattern classification can be used to restore some of the lost motor abilities. However, learning to control an advanced prosthesis can be a challenging task, but virtual and augmented reality (AR) provide means to create an engaging and motivating training. Methods In this study, we present a novel training framework that integrates virtual elements within a real scene (AR) while allowing the view from the first-person perspective. The framework was evaluated in 13 able-bodied subjects and a limb-deficient person divided into intervention (IG) and control (CG) groups. The IG received training by performing simulated clothespin task and both groups conducted a pre- and posttest with a real prosthesis. When training with the AR, the subjects received visual feedback on the generated grasping force. The main outcome measure was the number of pins that were successfully transferred within 20 min (task duration), while the number of dropped and broken pins were also registered. The participants were asked to score the difficulty of the real task (posttest), fun-factor and motivation, as well as the utility of the feedback. Results The performance (median/interquartile range) consistently increased during the training sessions (4/3 to 22/4). While the results were similar for the two groups in the pretest, the performance improved in the posttest only in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5 versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9) significantly fewer pins in the posttest compared to CG. The participants in IG assigned (mean ± std) significantly lower scores to the difficulty compared to CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3) and usefulness of feedback (8.5 ± 1.7). Conclusion The results demonstrated that the proposed AR system allows for the transfer of skills from the simulated to the real task while providing a positive user experience. The present study demonstrates the effectiveness and flexibility of the proposed AR framework. Importantly, the developed system is open source and available for download and further development. AU - Boschmann, Alexander AU - Neuhaus, Dorothee AU - Vogt, Sarah AU - Kaltschmidt, Christian AU - Platzner, Marco AU - Dosen, Strahinja ID - 30906 IS - 1 JF - Journal of NeuroEngineering and Rehabilitation KW - Health Informatics KW - Rehabilitation SN - 1743-0003 TI - Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis VL - 18 ER - TY - JOUR AU - Rodriguez, Alfonso AU - Otero, Andres AU - Platzner, Marco AU - De la Torre, Eduardo ID - 30907 JF - IEEE Transactions on Computers KW - Computational Theory and Mathematics KW - Hardware and Architecture KW - Theoretical Computer Science KW - Software SN - 0018-9340 TI - Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs ER - TY - CONF AU - Hansmeier, Tim ID - 29137 T2 - HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS ER - TY - GEN AB - Autonomous mobile robots are becoming increasingly more capable and widespread. Reliable Obstacle avoidance is an integral part of autonomous navigation. This involves real time interpretation and processing of a complex environment. Strict time and energy constraints of a mobile autonomous system make efficient computation extremely desirable. The benefits of employing Hardware/Software co-designed applications are obvious and significant. Hardware accelerators are used for efficient processing of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators, which can contain hundreds of small execution units, and can be used for Hardware/Software co-designed application. However, there is a reluctance when it comes to adoption of these devices in well established application domains, such as Robotics, due to a steep learning curve needed for FPGA application design. ReconROS has successfully bridged the gap between robotic and FPGA application development, by providing an intuitive, common development platform for robotic application development for FPGA. It does so by integrating Robotics Operating System(ROS) which is an industry and academia standard for robotics application development, with ReconOS, an operating system for re-configurable hardware. In this thesis an obstacle avoidance system is designed and implemented for an autonomous vehicle using ReconROS. The objectives of the thesis is to demonstrate and explore ReconROS integration within the ROS ecosystem and explore the design process within ReconROS framework, and to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing the resulting architectures for Latency and Power Consumption. AU - Sheikh, Muhammad Aamir ID - 29540 TI - Design and Implementation of a ReconROS-based Obstacle Avoidance System ER - TY - GEN AB - Robotics applications process large amounts of data in real-time and require compute platforms that provide high performance and energy-efficiency. FPGAs are well-suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this paper we present ReconROS, a framework that integrates the widely-used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach. AU - Lienen, Christian AU - Platzner, Marco ID - 22764 T2 - arXiv:2107.07208 TI - Design of Distributed Reconfigurable Robotics Systems with ReconROS ER -