--- _id: '10768' author: - first_name: Ines full_name: Ghribi, Ines last_name: Ghribi - first_name: Riadh full_name: Ben Abdallah, Riadh last_name: Ben Abdallah - first_name: Mohamed full_name: Khalgui, Mohamed last_name: Khalgui - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA). ; 2016:185-195.' apa: Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). New Co-design Methodology for Real-time Embedded Systems. In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) (pp. 185–195). bibtex: '@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={New Co-design Methodology for Real-time Embedded Systems}, booktitle={Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016}, pages={185–195} }' chicago: Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Co-Design Methodology for Real-Time Embedded Systems.” In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 185–95, 2016. ieee: I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Co-design Methodology for Real-time Embedded Systems,” in Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195. mla: Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–95. short: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.' date_created: 2019-07-10T12:07:56Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng page: 185-195 publication: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) status: public title: New Co-design Methodology for Real-time Embedded Systems type: conference user_id: '3118' year: '2016' ... --- _id: '10769' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Pierre-Emmanuel full_name: Gaillardon, Pierre-Emmanuel last_name: Gaillardon - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli citation: ama: Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908 apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2016). Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, PP(99), 1–1. https://doi.org/10.1109/TCAD.2016.2547908 bibtex: '@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, volume={PP}, DOI={10.1109/TCAD.2016.2547908}, number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1} }' chicago: 'Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP, no. 99 (2016): 1–1. https://doi.org/10.1109/TCAD.2016.2547908.' ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016. mla: Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908. short: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP (2016) 1–1. date_created: 2019-07-10T12:08:14Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/TCAD.2016.2547908 extern: '1' issue: '99' language: - iso: eng page: 1-1 publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publisher: IEEE status: public title: Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation type: journal_article user_id: '3118' volume: PP year: '2016' ... --- _id: '10781' author: - first_name: Sven full_name: Hermansen, Sven last_name: Hermansen citation: ama: Hermansen S. Custom Memory Controller for ReconOS. Paderborn University; 2016. apa: Hermansen, S. (2016). Custom Memory Controller for ReconOS. Paderborn University. bibtex: '@book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }' chicago: Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016. ieee: S. Hermansen, Custom Memory Controller for ReconOS. Paderborn University, 2016. mla: Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016. short: S. Hermansen, Custom Memory Controller for ReconOS, Paderborn University, 2016. date_created: 2019-07-10T12:13:16Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Custom Memory Controller for ReconOS type: bachelorsthesis user_id: '3118' year: '2016' ... --- _id: '12972' abstract: - lang: eng text: Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering. citation: ama: 'Lewis PR, Platzner M, Rinner B, Tørresen J, Yao X, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer; 2016. doi:10.1007/978-3-319-39675-0' apa: 'Lewis, P. R., Platzner, M., Rinner, B., Tørresen, J., & Yao, X. (Eds.). (2016). Self-aware Computing Systems: An Engineering Approach. Cham: Springer. https://doi.org/10.1007/978-3-319-39675-0' bibtex: '@book{Lewis_Platzner_Rinner_Tørresen_Yao_2016, place={Cham}, title={Self-aware Computing Systems: An Engineering Approach}, DOI={10.1007/978-3-319-39675-0}, publisher={Springer}, year={2016} }' chicago: 'Lewis, Peter R., Marco Platzner, Bernhard Rinner, Jim Tørresen, and Xin Yao, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer, 2016. https://doi.org/10.1007/978-3-319-39675-0.' ieee: 'P. R. Lewis, M. Platzner, B. Rinner, J. Tørresen, and X. Yao, Eds., Self-aware Computing Systems: An Engineering Approach. Cham: Springer, 2016.' mla: 'Lewis, Peter R., et al., editors. Self-Aware Computing Systems: An Engineering Approach. Springer, 2016, doi:10.1007/978-3-319-39675-0.' short: 'P.R. Lewis, M. Platzner, B. Rinner, J. Tørresen, X. Yao, eds., Self-Aware Computing Systems: An Engineering Approach, Springer, Cham, 2016.' date_created: 2019-08-27T13:39:43Z date_updated: 2022-01-06T06:51:27Z department: - _id: '78' doi: 10.1007/978-3-319-39675-0 editor: - first_name: Peter R. full_name: Lewis, Peter R. last_name: Lewis - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: Jim full_name: Tørresen, Jim last_name: Tørresen - first_name: Xin full_name: Yao, Xin last_name: Yao language: - iso: eng place: Cham publication_identifier: isbn: - '9783319396743' - '9783319396750' issn: - 1619-7127 publication_status: published publisher: Springer status: public title: 'Self-aware Computing Systems: An Engineering Approach' type: book_editor user_id: '398' year: '2016' ... --- _id: '15873' author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Georg full_name: Thombansen, Georg last_name: Thombansen - first_name: Florian full_name: Kraus, Florian last_name: Kraus - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312' apa: 'Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE. https://doi.org/10.1109/reconfig.2015.7393312' bibtex: '@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }' chicago: Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312. ieee: A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexiko City, Mexiko, 2016. mla: Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312. short: 'A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.' conference: location: Mexiko City, Mexiko name: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) date_created: 2020-02-11T07:48:56Z date_updated: 2022-01-06T06:52:38Z department: - _id: '78' doi: 10.1109/reconfig.2015.7393312 keyword: - Electromyography - Feature extraction - Delays - Hardware Pattern recognition - Prosthetics - High definition video language: - iso: eng publication: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) publication_identifier: isbn: - '9781467394062' publication_status: published publisher: IEEE status: public title: FPGA-based acceleration of high density myoelectric signal processing type: conference user_id: '49051' year: '2016' ... --- _id: '13151' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: Computer and Games. ; 2016.' apa: Graf, T., & Platzner, M. (2016). Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In Computer and Games. bibtex: '@inproceedings{Graf_Platzner_2016, title={Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}, booktitle={Computer and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }' chicago: Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” In Computer and Games, 2016. ieee: T. Graf and M. Platzner, “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search,” in Computer and Games, 2016. mla: Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016. short: 'T. Graf, M. Platzner, in: Computer and Games, 2016.' date_created: 2019-09-09T09:01:09Z date_updated: 2022-01-06T06:51:29Z department: - _id: '78' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Computer and Games status: public title: Using Deep Convolutional Neural Networks in Monte Carlo Tree Search type: conference user_id: '398' year: '2016' ... --- _id: '13152' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: IEEE Computational Intelligence and Games. ; 2016.' apa: Graf, T., & Platzner, M. (2016). Monte-Carlo Simulation Balancing Revisited. In IEEE Computational Intelligence and Games. bibtex: '@inproceedings{Graf_Platzner_2016, title={Monte-Carlo Simulation Balancing Revisited}, booktitle={IEEE Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }' chicago: Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” In IEEE Computational Intelligence and Games, 2016. ieee: T. Graf and M. Platzner, “Monte-Carlo Simulation Balancing Revisited,” in IEEE Computational Intelligence and Games, 2016. mla: Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016. short: 'T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016.' date_created: 2019-09-09T09:06:39Z date_updated: 2022-01-06T06:51:29Z department: - _id: '78' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: IEEE Computational Intelligence and Games status: public title: Monte-Carlo Simulation Balancing Revisited type: conference user_id: '398' year: '2016' ... --- _id: '132' abstract: - lang: eng text: Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910' apa: Wiersema, T., & Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) (pp. 1--8). https://doi.org/10.1109/ReCoSoC.2016.7533910 bibtex: '@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={10.1109/ReCoSoC.2016.7533910}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }' chicago: Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 1--8, 2016. https://doi.org/10.1109/ReCoSoC.2016.7533910. ieee: T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8. mla: Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910. short: 'T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.' date_created: 2017-10-17T12:41:17Z date_updated: 2022-01-06T06:51:30Z ddc: - '040' department: - _id: '78' doi: 10.1109/ReCoSoC.2016.7533910 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T13:02:30Z date_updated: 2018-03-21T13:02:30Z file_id: '1562' file_name: 132-07533910.pdf file_size: 911171 relation: main_file success: 1 file_date_updated: 2018-03-21T13:02:30Z has_accepted_license: '1' language: - iso: eng page: 1--8 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) status: public title: Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware type: conference user_id: '477' year: '2016' ... --- _id: '29' abstract: - lang: eng text: In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers citation: ama: 'Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13' apa: Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13 bibtex: '@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }' chicago: 'Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.' ieee: 'A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.' mla: Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13. short: 'A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.' date_created: 2017-07-26T15:07:06Z date_updated: 2023-09-26T13:25:38Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-26408-0_13 editor: - first_name: Dirk full_name: Koch, Dirk last_name: Koch - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Daniel full_name: Ziener, Daniel last_name: Ziener language: - iso: eng page: 227-244 place: Cham project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: FPGAs for Software Programmers publication_identifier: isbn: - 978-3-319-26406-6 - 978-3-319-26408-0 publication_status: published publisher: Springer International Publishing quality_controlled: '1' status: public title: ReconOS type: book_chapter user_id: '15278' year: '2016' ... --- _id: '156' abstract: - lang: eng text: Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8' apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8 bibtex: '@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }' chicago: 'Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.' ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.' mla: Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8. short: 'A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.' date_created: 2017-10-17T12:41:22Z date_updated: 2023-09-26T13:27:44Z ddc: - '040' department: - _id: '518' - _id: '27' - _id: '78' doi: 10.1007/978-3-319-39675-0_8 file: - access_level: closed content_type: application/pdf creator: aloesch date_created: 2018-11-14T13:20:32Z date_updated: 2018-11-14T13:20:32Z file_id: '5613' file_name: chapter8.pdf file_size: 833054 relation: main_file success: 1 file_date_updated: 2018-11-14T13:20:32Z has_accepted_license: '1' language: - iso: eng page: 145-165 place: Cham project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Self-aware Computing Systems publisher: Springer International Publishing quality_controlled: '1' series_title: Natural Computing Series (NCS) status: public title: Self-aware Compute Nodes type: book_chapter user_id: '15278' year: '2016' ...