---
_id: '168'
abstract:
- lang: eng
text: The use of heterogeneous computing resources, such as Graphic Processing Units
or other specialized coprocessors, has become widespread in recent years because
of their per- formance and energy efficiency advantages. Approaches for managing
and scheduling tasks to heterogeneous resources are still subject to research.
Although queuing systems have recently been extended to support accelerator resources,
a general solution that manages heterogeneous resources at the operating system-
level to exploit a global view of the system state is still missing.In this paper
we present a user space scheduler that enables task scheduling and migration on
heterogeneous processing resources in Linux. Using run queues for available resources
we perform scheduling decisions based on the system state and on task characterization
from earlier measurements. With a pro- gramming pattern that supports the integration
of checkpoints into applications, we preempt tasks and migrate them between three
very different compute resources. Considering static and dynamic workload scenarios,
we show that this approach can gain up to 17% performance, on average 7%, by effectively
avoiding idle resources. We demonstrate that a work-conserving strategy without
migration is no suitable alternative.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling
with task migration for a heterogeneous compute node in the data center. In: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE). EDA Consortium / IEEE; 2016:912-917.'
apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center.
Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 912–917.
bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center},
booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim
and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco},
year={2016}, pages={912–917} }'
chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco
Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous
Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation
& Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium
/ IEEE, 2016.
ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center,”
in Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2016, pp. 912–917.
mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for
a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design,
Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium
/ IEEE, 2016, pp. 912–17.
short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE), EDA Consortium / IEEE, 2016, pp. 912–917.'
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:27:00Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:41:55Z
date_updated: 2018-03-21T12:41:55Z
file_id: '1541'
file_name: 168-07459438.pdf
file_size: 261356
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:41:55Z
has_accepted_license: '1'
language:
- iso: eng
page: 912-917
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Performance-centric scheduling with task migration for a heterogeneous compute
node in the data center
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '269'
abstract:
- lang: eng
text: Proof-carrying hardware is an approach that has recently been proposed for
the efficient verification of reconfigurable modules. We present an application
of proof-carrying hardware to guarantee the correct functionality of dynamically
reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip
with an embedded virtual FPGA fabric. This setup allows us to leverage open source
FPGA synthesis and backend tools to produce FPGA configuration bitstreams with
an open format and, thus, to demonstrate and experimentally evaluate proof-carrying
hardware at the bitstream level.
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Sen
full_name: Wu, Sen
last_name: Wu
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image
Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings
of the International Symposium in Reconfigurable Computing (ARC). LNCS. ;
2015:365--372. doi:10.1007/978-3-319-16214-0_32'
apa: Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of
Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach.
In Proceedings of the International Symposium in Reconfigurable Computing (ARC)
(pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32
bibtex: '@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly
Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying
Hardware Approach}, DOI={10.1007/978-3-319-16214-0_32},
booktitle={Proceedings of the International Symposium in Reconfigurable Computing
(ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015},
pages={365--372}, collection={LNCS} }'
chicago: Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification
of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware
Approach.” In Proceedings of the International Symposium in Reconfigurable
Computing (ARC), 365--372. LNCS, 2015. https://doi.org/10.1007/978-3-319-16214-0_32.
ieee: T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable
Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings
of the International Symposium in Reconfigurable Computing (ARC), 2015, pp.
365--372.
mla: Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing
Modules Based on a Proof-Carrying Hardware Approach.” Proceedings of the International
Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.
short: 'T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium
in Reconfigurable Computing (ARC), 2015, pp. 365--372.'
date_created: 2017-10-17T12:41:44Z
date_updated: 2022-01-06T06:57:30Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1007/978-3-319-16214-0_32
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T09:32:42Z
date_updated: 2018-03-21T09:32:42Z
file_id: '1477'
file_name: 269-paper_53.pdf
file_size: 344309
relation: main_file
success: 1
file_date_updated: 2018-03-21T09:32:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 365--372
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the International Symposium in Reconfigurable Computing
(ARC)
series_title: LNCS
status: public
title: On-The-Fly Verification of Reconfigurable Image Processing Modules based on
a Proof-Carrying Hardware Approach
type: conference
user_id: '477'
year: '2015'
...
---
_id: '3364'
author:
- first_name: Christoph
full_name: Knorr, Christoph
last_name: Knorr
citation:
ama: Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten.
Universität Paderborn; 2015.
apa: Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn.
bibtex: '@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in
heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph},
year={2015} }'
chicago: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn, 2015.
ieee: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten.
Universität Paderborn, 2015.
mla: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn, 2015.
short: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten,
Universität Paderborn, 2015.
date_created: 2018-06-26T14:06:07Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten
type: bachelorsthesis
user_id: '477'
year: '2015'
...
---
_id: '1772'
author:
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Xin
full_name: Yao, Xin
last_name: Yao
citation:
ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest
Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205
apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20.
https://doi.org/10.1109/MC.2015.205
bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205},
number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen,
Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }'
chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015):
18–20. https://doi.org/10.1109/MC.2015.205.'
ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems
– Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20,
2015.
mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s
Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015,
pp. 18–20, doi:10.1109/MC.2015.205.
short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.
date_created: 2018-03-23T14:06:12Z
date_updated: 2022-01-06T06:53:19Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MC.2015.205
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T15:47:45Z
date_updated: 2018-11-02T15:47:45Z
file_id: '5313'
file_name: 07163237.pdf
file_size: 5605009
relation: main_file
success: 1
file_date_updated: 2018-11-02T15:47:45Z
has_accepted_license: '1'
intvolume: ' 48'
issue: '7'
keyword:
- self-awareness
- self-expression
language:
- iso: eng
page: 18-20
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: IEEE Computer
publisher: IEEE Computer Society
status: public
title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction
type: journal_article
user_id: '16153'
volume: 48
year: '2015'
...
---
_id: '10615'
author:
- first_name: Abdullah Fathi
full_name: Ahmed, Abdullah Fathi
last_name: Ahmed
citation:
ama: Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015.
apa: Ahmed, A. F. (2015). Self-Optimizing Organic Cache. Paderborn University.
bibtex: '@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn
University}, author={Ahmed, Abdullah Fathi}, year={2015} }'
chicago: Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn
University, 2015.
ieee: A. F. Ahmed, Self-Optimizing Organic Cache. Paderborn University, 2015.
mla: Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University,
2015.
short: A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015.
date_created: 2019-07-10T09:25:13Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Self-Optimizing Organic Cache
type: mastersthesis
user_id: '3118'
year: '2015'
...
---
_id: '10624'
abstract:
- lang: eng
text: "The use of heterogeneous computing resources, such as graphics processing
units or other specialized co-processors, has become widespread in recent years
because of their performance and energy efficiency advantages. Operating system
approaches that are limited to optimizing CPU usage are no longer sufficient for
the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling
task preemption on these architectures and migration of tasks between different
resource types at run-time is not only key to improving the performance and energy
consumption but also to enabling automatic scheduling methods for heterogeneous
compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management
of heterogeneous resources and enabling tasks to migrate between diverse hardware.
It provides fundamental work towards future operating systems by discussing implications,
limitations, and chances of the heterogeneity and introducing solutions for energy-
and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous
systems by the use of a centralized scheduler are presented that show benefits
over existing approaches in varying case studies."
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
citation:
ama: 'Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing. Berlin: Logos Verlag Berlin GmbH; 2015.'
apa: 'Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of
Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag
Berlin GmbH}, author={Beisel, Tobias}, year={2015} }'
chicago: 'Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.'
ieee: 'T. Beisel, Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.'
mla: Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Logos Verlag Berlin GmbH, 2015.
short: T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing, Logos Verlag Berlin GmbH, Berlin, 2015.
date_created: 2019-07-10T09:36:58Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
- _id: '27'
- _id: '518'
language:
- iso: eng
page: '183'
place: Berlin
project:
- _id: '30'
grant_number: 01|H11004
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication_identifier:
isbn:
- 978-3-8325-4155-2
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing
type: dissertation
user_id: '3118'
year: '2015'
...
---
_id: '10668'
author:
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
citation:
ama: Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University; 2015.
apa: Hangmann, H. (2015). Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University.
bibtex: '@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for
FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015}
}'
chicago: Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA
Devices. Paderborn University, 2015.
ieee: H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University, 2015.
mla: Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University, 2015.
short: H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn
University, 2015.
date_created: 2019-07-10T11:15:13Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Evolution of Heat Flow Prediction Models for FPGA Devices
type: mastersthesis
user_id: '3118'
year: '2015'
...
---
_id: '10671'
author:
- first_name: Christian
full_name: Haupt, Christian
last_name: Haupt
citation:
ama: Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen.
Paderborn University; 2015.
apa: Haupt, C. (2015). Computer Vision basierte Klassifikation von HD EMG Signalen.
Paderborn University.
bibtex: '@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD
EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015}
}'
chicago: Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG
Signalen. Paderborn University, 2015.
ieee: C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen.
Paderborn University, 2015.
mla: Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen.
Paderborn University, 2015.
short: C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn
University, 2015.
date_created: 2019-07-10T11:17:57Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: Computer Vision basierte Klassifikation von HD EMG Signalen
type: mastersthesis
user_id: '3118'
year: '2015'
...
---
_id: '10673'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Abdullah Fathi
full_name: Ahmed, Abdullah Fathi
last_name: Ahmed
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf.
Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178'
apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings. In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178
bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178},
booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
pages={1–7} }'
chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.
ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA
Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.
mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems
(AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
mappings
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10693'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
citation:
ama: 'Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network
Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and
Evolutionary Computation (GECCO). ACM; 2015:409-416.'
apa: Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization
for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic
and Evolutionary Computation (GECCO) (pp. 409–416). ACM.
bibtex: '@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences
Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing},
booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann,
Paul and Shen, Cong}, year={2015}, pages={409–416} }'
chicago: Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization
for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In Genetic
and Evolutionary Computation (GECCO), 409–16. ACM, 2015.
ieee: P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network
Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and
Evolutionary Computation (GECCO), 2015, pp. 409–416.
mla: Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for
Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic
and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.
short: 'P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO),
ACM, 2015, pp. 409–416.'
date_created: 2019-07-10T11:30:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
page: 409-416
publication: Genetic and Evolutionary Computation (GECCO)
publisher: ACM
status: public
title: Generator Start-up Sequences Optimization for Network Restoration Using Genetic
Algorithm and Simulated Annealing
type: conference
user_id: '3118'
year: '2015'
...