---
_id: '328'
abstract:
- lang: eng
text: The ReconOS operating system for reconfigurable computing offers a unified
multi-threaded programming model and operating system services for threads executing
in software and threads mapped to reconfigurable hardware. The operating system
interface allows hardware threads to interact with software threads using well-known
mechanisms such as semaphores, mutexes, condition variables, and message queues.
By semantically integrating hardware accelerators into a standard operating system
environment, ReconOS allows for rapid design space exploration, supports a structured
application development process and improves the portability of applications
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for
Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &
Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS
- An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1},
journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus
and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={60–71} }'
chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner,
Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach
for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.'
ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable
Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.'
mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable
Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl,
IEEE Micro 34 (2014) 60–71.
date_created: 2017-10-17T12:41:55Z
date_updated: 2023-09-26T13:32:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MM.2013.110
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:31:40Z
date_updated: 2018-03-20T07:31:40Z
file_id: '1426'
file_name: 328-plessl14_micro_01.pdf
file_size: 1877185
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:31:40Z
has_accepted_license: '1'
intvolume: ' 34'
issue: '1'
language:
- iso: eng
page: 60-71
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: IEEE Micro
publisher: IEEE
quality_controlled: '1'
status: public
title: ReconOS - An Operating System Approach for Reconfigurable Computing
type: journal_article
user_id: '15278'
volume: 34
year: '2014'
...
---
_id: '1778'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Pogliani, Marcello
last_name: Pogliani
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27'
apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G.
F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management
in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp.
on Parallel and Distributed Processing with Applications (ISPA), 142–149.
https://doi.org/10.1109/ISPA.2014.27'
bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014,
title={Runtime Resource Management in Heterogeneous System Architectures: The
SAVE Approach}, DOI={10.1109/ISPA.2014.27},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello
and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin
Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149}
}'
chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl,
Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini.
“Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.'
ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.'
mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.'
short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M.
D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed
Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.'
date_created: 2018-03-26T13:40:14Z
date_updated: 2023-09-26T13:35:40Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISPA.2014.27
language:
- iso: eng
page: 142-149
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE
Approach'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1780'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Copolla, Marcello
last_name: Copolla
- first_name: Karim
full_name: Djafarian, Karim
last_name: Djafarian
- first_name: George
full_name: Koranaros, George
last_name: Koranaros
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Michele
full_name: Paolino, Michele
last_name: Paolino
- first_name: Oliver
full_name: Pell, Oliver
last_name: Pell
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource
management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38'
apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino,
M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE:
Towards efficient resource management in heterogeneous system architectures. Proc.
Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications
(ARC). https://doi.org/10.1007/978-3-319-05960-0_38'
bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D.
Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management
in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38},
booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools
and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and
Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio
and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio,
Marco and Bolchini, Cristiana}, year={2014} }'
chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros,
Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio,
and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous
System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures,
Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.'
ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management
in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.'
mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management
in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.'
short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino,
O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014.'
date_created: 2018-03-26T13:45:35Z
date_updated: 2023-09-26T13:36:20Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_38
language:
- iso: eng
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and
Applications (ARC)'
publisher: Springer
quality_controlled: '1'
status: public
title: 'SAVE: Towards efficient resource management in heterogeneous system architectures'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1779'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain
Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture
News. 2014;41(5):65-70. doi:10.1145/2641361.2641372
apa: Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH
Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372
bibtex: '@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41},
DOI={10.1145/2641361.2641372},
number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM},
author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014},
pages={65–70} }'
chicago: 'Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite
Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM
SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.'
ieee: 'H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time
Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer
Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.'
mla: Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations
with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture
News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.
short: H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News
41 (2014) 65–70.
date_created: 2018-03-26T13:42:34Z
date_updated: 2023-09-26T13:35:58Z
department:
- _id: '27'
- _id: '518'
- _id: '61'
- _id: '78'
doi: 10.1145/2641361.2641372
intvolume: ' 41'
issue: '5'
keyword:
- funding-maxup
- tet_topic_hpc
language:
- iso: eng
page: 65-70
publication: ACM SIGARCH Computer Architecture News
publication_identifier:
issn:
- 0163-5964
publisher: ACM
quality_controlled: '1'
status: public
title: Accelerating Finite Difference Time Domain Simulations with Reconfigurable
Dataflow Computers
type: journal_article
user_id: '15278'
volume: 41
year: '2014'
...
---
_id: '11619'
abstract:
- lang: eng
text: "Reconfigurable circuit devices have opened up a fundamentally new way of
creating adaptable systems. Combined with artificial evolution, reconfigurable
circuits allow an elegant adaptation approach to compensating for changes in the
distribution of input data, computational resource errors, and variations in resource
requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded
astonishing results for traditional engineering challenges and has discovered
intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn
this thesis, we present new and fundamental work on Evolvable Hardware motivated
by the insight that Evolvable Hardware needs to compensate for events with different
change rates. To solve the challenge of different adaptation speeds, we propose
a unified adaptation approach based on multi-objective evolution, evolving and
propagating candidate solutions that are diverse in objectives that may experience
radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic
Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective
optimization by introducing a meaningful recombination operator. We improve the
scalability of CGP by objectives scaling, periodization of local- and global-search
algorithms, and the automatic acquisition and reuse of subfunctions using age-
and cone-based techniques. We validate our methods on the applications of adaptation
of hardware classifiers to resource changes, recognition of muscular signals for
prosthesis control and optimization of processor caches."
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: 'Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by
Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann,
Paul}, year={2013} }'
chicago: 'Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Logos Verlag Berlin GmbH, 2013.
short: P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2019-07-11T11:51:51Z
date_updated: 2022-01-06T06:51:04Z
department:
- _id: '78'
language:
- iso: eng
page: '249'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3530-8
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Adapting Hardware Systems by Means of Multi-Objective Evolution
type: dissertation
user_id: '3118'
year: '2013'
...
---
_id: '1786'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind
Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530'
apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530
bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530},
booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE},
author={Kasap, Server and Redif, Soydan}, year={2013} }'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing
and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.
ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications
Conf. (SUI), 2013.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.
short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013.'
date_created: 2018-03-26T14:48:53Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/SIU.2013.6531530
publication: Proc. IEEE Signal Processing and Communications Conf. (SUI)
publisher: IEEE
status: public
title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1792'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing
the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans
on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069
apa: Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3),
522–536. https://doi.org/10.1109/TVLSI.2013.2248069
bibtex: '@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices},
volume={22}, DOI={10.1109/TVLSI.2013.2248069},
number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems},
publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536}
}'
chicago: 'Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array
Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial
Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22,
no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069.'
ieee: S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for
Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, pp. 522–536, 2013.
mla: Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.
short: S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems
22 (2013) 522–536.
date_created: 2018-03-26T15:15:03Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/TVLSI.2013.2248069
intvolume: ' 22'
issue: '3'
page: 522-536
publication: IEEE Trans. on Very Large Scale Integration (VLSI) Systems
publisher: IEEE
status: public
title: Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue
Decomposition of Para-Hermitian Polynomial Matrices
type: journal_article
user_id: '24135'
volume: 22
year: '2013'
...
---
_id: '501'
abstract:
- lang: eng
text: 'Handling run-time dynamics on embedded system-on-chip architectures has become
more challenging over the years. On the one hand, the impact of workload and physical
dynamics on the system behavior has dramatically increased. On the other hand,
embedded architectures have become more complex as they have evolved from single-processor
systems over multi-processor systems to hybrid multi-core platforms.Static design-time
techniques no longer provide suitable solutions to deal with the run-time dynamics
of today''s embedded systems. Therefore, system designers have to apply run-time
solutions, which have hardly been investigated for hybrid multi-core platforms.In
this thesis, we present fundamental work in the new area of run-time management
on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive
hybrid multi-core system, that combines heterogeneous processors, reconfigurable
hardware cores, and monitoring cores on a single chip. Using self-adaptation on
thread-level, our hybrid multi-core systems can effectively perform performance
and thermal management autonomously at run-time. '
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
citation:
ama: 'Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Happe, M. (2013). Performance and thermal management on self-adaptive hybrid
multi-cores. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Happe_2013, place={Berlin}, title={Performance and thermal management
on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe,
Markus}, year={2013} }'
chicago: 'Happe, Markus. Performance and Thermal Management on Self-Adaptive
Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid
Multi-Cores. Logos Verlag Berlin GmbH, 2013.
short: M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2017-10-17T12:42:30Z
date_updated: 2022-01-06T07:01:34Z
department:
- _id: '78'
language:
- iso: eng
page: '220'
place: Berlin
project:
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publication_identifier:
isbn:
- 978-3-8325-3425-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
related_material:
link:
- relation: confirmation
url: https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id=
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Performance and thermal management on self-adaptive hybrid multi-cores
type: dissertation
user_id: '477'
year: '2013'
...