---
_id: '13642'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Giefers H, Platzner M. A Self-Reconfigurable Lightweight Interconnect for
Scalable Processor Fabrics. In: Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press;
2010.'
apa: Giefers, H., & Platzner, M. (2010). A Self-Reconfigurable Lightweight Interconnect
for Scalable Processor Fabrics. In Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
bibtex: '@inproceedings{Giefers_Platzner_2010, title={A Self-Reconfigurable Lightweight
Interconnect for Scalable Processor Fabrics}, booktitle={Proceedings of the 10th
International Conference on Engineering of Reconfigurable Systems and Algorithms
(ERSA)}, publisher={CSREA Press}, author={Giefers, Heiner and Platzner, Marco},
year={2010} }'
chicago: Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight
Interconnect for Scalable Processor Fabrics.” In Proceedings of the 10th International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA).
CSREA Press, 2010.
ieee: H. Giefers and M. Platzner, “A Self-Reconfigurable Lightweight Interconnect
for Scalable Processor Fabrics,” in Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010.
mla: Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect
for Scalable Processor Fabrics.” Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2010.
short: 'H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.'
date_created: 2019-10-04T22:37:54Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 10th International Conference on Engineering of Reconfigurable
Systems and Algorithms (ERSA)
publisher: CSREA Press
status: public
title: A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
type: conference
user_id: '398'
year: '2010'
...
---
_id: '2223'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
citation:
ama: 'Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking
for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press;
2010:225-231.'
apa: Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010).
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware.
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
225–231.
bibtex: '@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards
Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller,
Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }'
chicago: Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard
Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable
Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 225–31. CSREA Press, 2010.
ieee: E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive
Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2010, pp. 225–231.
mla: Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based
on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.
short: 'E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2010, pp. 225–231.'
date_created: 2018-04-05T16:27:13Z
date_updated: 2023-09-26T13:48:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 225-231
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2216'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization.
In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig).
IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19'
apa: Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time
Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs
(ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19
bibtex: '@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning
the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19},
booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian},
year={2010}, pages={67–72} }'
chicago: 'Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010.
https://doi.org/10.1109/ReConFig.2010.19.'
ieee: 'M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor
Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig),
2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19.'
mla: Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.'
date_created: 2018-04-05T14:48:51Z
date_updated: 2023-09-26T13:47:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2010.19
language:
- iso: eng
page: 67-72
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Pruning the Design Space for Just-In-Time Processor Customization
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2224'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:144-150.'
apa: Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking
Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 144–150.
bibtex: '@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library
with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz
and Plessl, Christian}, year={2010}, pages={144–150} }'
chicago: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with
Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.
ieee: M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,”
in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 2010, pp. 144–150.
mla: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking
Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.'
date_created: 2018-04-05T16:28:38Z
date_updated: 2023-09-26T13:48:59Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 144-150
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: An Open Source Circuit Library with Benchmarking Facilities
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2220'
author:
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Andrews D, Plessl C. Configurable Processor Architectures: History and Trends.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:165.'
apa: 'Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures:
History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165.'
bibtex: '@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures:
History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David
and Plessl, Christian}, year={2010}, pages={165} }'
chicago: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165. CSREA Press, 2010.'
ieee: 'D. Andrews and C. Plessl, “Configurable Processor Architectures: History
and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 2010, p. 165.'
mla: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
short: 'D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
date_created: 2018-04-05T14:57:07Z
date_updated: 2023-09-26T13:47:33Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: '165'
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Configurable Processor Architectures: History and Trends'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2222'
citation:
ama: Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.
apa: Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &
Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press.
bibtex: '@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, year={2010} }'
chicago: Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee,
Christian Plessl, and Greg Stitt, eds. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
ieee: T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
mla: Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
short: T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds.,
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2010.
date_created: 2018-04-05T15:00:49Z
date_updated: 2023-09-26T13:48:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Toomas P.
full_name: Plaks, Toomas P.
last_name: Plaks
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Ronald
full_name: DeMara, Ronald
last_name: DeMara
- first_name: Herman
full_name: Lam, Herman
last_name: Lam
- first_name: Jooheung
full_name: Lee, Jooheung
last_name: Lee
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Greg
full_name: Stitt, Greg
last_name: Stitt
language:
- iso: eng
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
type: conference_editor
user_id: '15278'
year: '2010'
...
---
_id: '2226'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Manuel
full_name: Niekamp, Manuel
last_name: Niekamp
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent
Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc.
Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP).
IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798'
apa: Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing
for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.
Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798
bibtex: '@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators}, DOI={10.1109/ASAP.2010.5540798},
booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias
and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }'
chicago: Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures,
and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798.
ieee: 'T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for
Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”
in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798.'
mla: Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration
in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010,
pp. 65–72, doi:10.1109/ASAP.2010.5540798.
short: 'T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp.
65–72.'
date_created: 2018-04-05T16:39:34Z
date_updated: 2023-09-26T13:49:21Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2010.5540798
language:
- iso: eng
page: 65-72
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)
publication_identifier:
isbn:
- 978-1-4244-6965-9
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Using Shared Library Interposing for Transparent Acceleration in Systems with
Heterogeneous Hardware Accelerators
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2206'
author:
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes
for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future
(FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341'
apa: Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010).
Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network
of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341
bibtex: '@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable
Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341},
booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)},
publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno
and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }'
chicago: Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian
Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom
Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341.
ieee: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable
Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the
Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.'
mla: Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc.
IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp.
372–76, doi:10.1109/GLOCOMW.2010.5700341.
short: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE
Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.'
date_created: 2018-04-04T09:36:16Z
date_updated: 2023-09-26T13:51:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/GLOCOMW.2010.5700341
language:
- iso: eng
page: 372-376
publication: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)
publication_identifier:
isbn:
- 978-1-4244-8864-3
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconfigurable Nodes for Future Networks
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2228'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the
Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds.
Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA). ; 2010.'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance
Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami
& S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping
(WARP), International Symposium on Computer Architecture (ISCA).
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance
Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc.
Workshop on Architectural Research Prototyping (WARP), International Symposium
on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and
Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee,
Sandra}, year={2010} }'
chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation for the Exploration of CPU-Accelerator Architectures.”
In Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra
Larrabee, 2010.
ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on
Architectural Research Prototyping (WARP), International Symposium on Computer
Architecture (ISCA), 2010.
mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator
Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP),
International Symposium on Computer Architecture (ISCA), edited by Omar Hammami
and Sandra Larrabee, 2010.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee
(Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), 2010.'
date_created: 2018-04-05T16:43:04Z
date_updated: 2023-09-26T13:50:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Omar
full_name: Hammami, Omar
last_name: Hammami
- first_name: Sandra
full_name: Larrabee, Sandra
last_name: Larrabee
language:
- iso: eng
publication: Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA)
quality_controlled: '1'
status: public
title: Performance Estimation for the Exploration of CPU-Accelerator Architectures
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '10639'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Michael
full_name: Winkler, Michael
last_name: Winkler
citation:
ama: 'Boschmann A, Kaufmann P, Platzner M, Winkler M. Towards multi-movement hand
prostheses: Combining adaptive classification with high precision sockets. In:
Proc. Technically Assisted Rehabilitation (TAR). ; 2009.'
apa: 'Boschmann, A., Kaufmann, P., Platzner, M., & Winkler, M. (2009). Towards
multi-movement hand prostheses: Combining adaptive classification with high precision
sockets. In Proc. Technically Assisted Rehabilitation (TAR).'
bibtex: '@inproceedings{Boschmann_Kaufmann_Platzner_Winkler_2009, title={Towards
multi-movement hand prostheses: Combining adaptive classification with high precision
sockets}, booktitle={Proc. Technically Assisted Rehabilitation (TAR)}, author={Boschmann,
Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}, year={2009}
}'
chicago: 'Boschmann, Alexander, Paul Kaufmann, Marco Platzner, and Michael Winkler.
“Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with
High Precision Sockets.” In Proc. Technically Assisted Rehabilitation (TAR),
2009.'
ieee: 'A. Boschmann, P. Kaufmann, M. Platzner, and M. Winkler, “Towards multi-movement
hand prostheses: Combining adaptive classification with high precision sockets,”
in Proc. Technically Assisted Rehabilitation (TAR), 2009.'
mla: 'Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining
Adaptive Classification with High Precision Sockets.” Proc. Technically Assisted
Rehabilitation (TAR), 2009.'
short: 'A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically
Assisted Rehabilitation (TAR), 2009.'
date_created: 2019-07-10T11:03:25Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. Technically Assisted Rehabilitation (TAR)
status: public
title: 'Towards multi-movement hand prostheses: Combining adaptive classification
with high precision sockets'
type: conference
user_id: '3118'
year: '2009'
...