---
_id: '13637'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Giefers H, Platzner M. Program-driven Fine-grained Power Management for the
Reconfigurable Mesh. In: Proceedings of the 19th International Workshop on
Field Programmable Logic and Applications (FPL) . IEEE; 2009.'
apa: Giefers, H., & Platzner, M. (2009). Program-driven Fine-grained Power Management
for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) . IEEE.
bibtex: '@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained
Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th
International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE},
author={Giefers, Heiner and Platzner, Marco}, year={2009} }'
chicago: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power
Management for the Reconfigurable Mesh.” In Proceedings of the 19th International
Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009.
ieee: H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management
for the Reconfigurable Mesh,” in Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) , 2009.
mla: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management
for the Reconfigurable Mesh.” Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) , IEEE, 2009.
short: 'H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) , IEEE, 2009.'
date_created: 2019-10-04T22:22:02Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: 'Proceedings of the 19th International Workshop on Field Programmable
Logic and Applications (FPL) '
publisher: IEEE
status: public
title: Program-driven Fine-grained Power Management for the Reconfigurable Mesh
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13638'
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework
with runtime HW/SW repartitioning. In: Proceedings of the 2009 International
Conference on Field-Programmable Technology (FPT). IEEE; 2009. doi:10.1109/fpt.2009.5377645'
apa: Happe, M., Lübbers, E., & Platzner, M. (2009). An adaptive Sequential Monte
Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009
International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/fpt.2009.5377645
bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential
Monte Carlo framework with runtime HW/SW repartitioning}, DOI={10.1109/fpt.2009.5377645},
booktitle={Proceedings of the 2009 International Conference on Field-Programmable
Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and
Platzner, Marco}, year={2009} }'
chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential
Monte Carlo Framework with Runtime HW/SW Repartitioning.” In Proceedings of
the 2009 International Conference on Field-Programmable Technology (FPT).
IEEE, 2009. https://doi.org/10.1109/fpt.2009.5377645.
ieee: M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo
framework with runtime HW/SW repartitioning,” in Proceedings of the 2009 International
Conference on Field-Programmable Technology (FPT), 2009.
mla: Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime
HW/SW Repartitioning.” Proceedings of the 2009 International Conference on
Field-Programmable Technology (FPT), IEEE, 2009, doi:10.1109/fpt.2009.5377645.
short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International
Conference on Field-Programmable Technology (FPT), IEEE, 2009.'
date_created: 2019-10-04T22:22:52Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpt.2009.5377645
language:
- iso: eng
publication: Proceedings of the 2009 International Conference on Field-Programmable
Technology (FPT)
publication_identifier:
isbn:
- '9781424443758'
publication_status: published
publisher: IEEE
status: public
title: An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13639'
author:
- first_name: Stephanie
full_name: Drzevitzky, Stephanie
last_name: Drzevitzky
- first_name: Uwe
full_name: Kastens, Uwe
last_name: Kastens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime
Verification of Reconfigurable Modules. In: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2009.'
apa: 'Drzevitzky, S., Kastens, U., & Platzner, M. (2009). Proof-carrying Hardware:
Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the
International Conference on ReConFigurable Computing and FPGAs (ReConFig).
IEEE.'
bibtex: '@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying
Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner,
Marco}, year={2009} }'
chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying
Hardware: Towards Runtime Verification of Reconfigurable Modules.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig).
IEEE, 2009.'
ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards
Runtime Verification of Reconfigurable Modules,” in Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009.'
mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification
of Reconfigurable Modules.” Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.'
short: 'S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.'
date_created: 2019-10-04T22:25:10Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
status: public
title: 'Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules'
type: conference
user_id: '398'
year: '2009'
...
---
_id: '2350'
abstract:
- lang: eng
text: 'Mapping applications that consist of a collection of cores to FPGA accelerators
and optimizing their performance is a challenging task in high performance reconfigurable
computing. We present IMORC, an architectural template and highly versatile on-chip
interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which
allows for flexibly composing accelerators from cores running at full speed within
their own clock domains, thus facilitating the re-use of cores and portability.
Further, IMORC inserts performance counters for monitoring runtime data. In this
paper, we first introduce the IMORC architectural template and the on-chip interconnect,
and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor
thinning problem on an XD1000 reconfigurable computing system. Using IMORC''s
monitoring infrastructure, we gain insights into the data-dependent behavior of
the application which, in turn, allow for optimizing the accelerator. '
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring
and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int.
Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer
Society; 2009:275-278. doi:10.1109/FCCM.2009.25'
apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.
Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM),
275–278. https://doi.org/10.1109/FCCM.2009.25'
bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing},
DOI={10.1109/FCCM.2009.25},
booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian
and Platzner, Marco}, year={2009}, pages={275–278} }'
chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.”
In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM),
275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.'
ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring
and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int.
Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278,
doi: 10.1109/FCCM.2009.25.'
mla: 'Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization
for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable
Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78,
doi:10.1109/FCCM.2009.25.'
short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable
Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.'
date_created: 2018-04-16T15:05:52Z
date_updated: 2023-09-26T13:51:44Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2009.25
keyword:
- IMORC
- interconnect
- performance
language:
- iso: eng
page: 275-278
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publication_identifier:
isbn:
- 978-1-4244-4450-2
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance
Reconfigurable Computing'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2262'
abstract:
- lang: eng
text: 'In this work we present EvoCache, a novel approach for implementing application-specific
caches. The key innovation of EvoCache is to make the function that maps memory
addresses from the CPU address space to cache indices programmable. We support
arbitrary Boolean mapping functions that are implemented within a small reconfigurable
logic fabric. For finding suitable cache mapping functions we rely on techniques
from the evolvable hardware domain and utilize an evolutionary optimization procedure.
We evaluate the use of EvoCache in an embedded processor for two specific applications
(JPEG and BZIP2 compression) with respect to execution time, cache miss rate and
energy consumption. We show that the evolvable hardware approach for optimizing
the cache functions not only significantly improves the cache performance for
the training data used during optimization, but that the evolved mapping functions
generalize very well. Compared to a conventional cache architecture, EvoCache
applied to test data achieves a reduction in execution time of up to 14.31% for
JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70%
for BZIP2). We also discuss the integration of EvoCache into the operating system
and show that the area and delay overheads introduced by EvoCache are acceptable. '
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation
of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems
(AHS). IEEE Computer Society; 2009:11-18.'
apa: 'Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific
Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 11–18.'
bibtex: '@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA,
USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc.
NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer
Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009},
pages={11–18} }'
chicago: 'Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific
Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.'
ieee: 'P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific
Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 2009, pp. 11–18.'
mla: 'Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache
Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS),
IEEE Computer Society, 2009, pp. 11–18.'
short: 'P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive
Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009,
pp. 11–18.'
date_created: 2018-04-06T15:18:24Z
date_updated: 2023-09-26T13:53:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- EvoCache
- evolvable hardware
- computer architecture
language:
- iso: eng
page: 11-18
place: Los Alamitos, CA, USA
publication: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'EvoCaches: Application-specific Adaptation of Cache Mapping'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2238'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization
for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on
ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124.
doi:10.1109/ReConFig.2009.32'
apa: Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication
Performance Characterization for Reconfigurable Accelerator Design on the XD1000.
Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124.
https://doi.org/10.1109/ReConFig.2009.32
bibtex: '@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos,
CA, USA}, title={Communication Performance Characterization for Reconfigurable
Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32},
booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and
Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }'
chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication
Performance Characterization for Reconfigurable Accelerator Design on the XD1000.”
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24.
Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.'
ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance
Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc.
Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124,
doi: 10.1109/ReConFig.2009.32.'
mla: Schumacher, Tobias, et al. “Communication Performance Characterization for
Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable
Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.
short: 'T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable
Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA,
2009, pp. 119–124.'
date_created: 2018-04-05T17:11:28Z
date_updated: 2023-09-26T13:52:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2009.32
keyword:
- IMORC
- graphics
language:
- iso: eng
page: 119-124
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publication_identifier:
isbn:
- 978-0-7695-3917-1
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Communication Performance Characterization for Reconfigurable Accelerator Design
on the XD1000
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2261'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor
Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL). IEEE; 2009:338-344.'
apa: Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th
Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf.
on Field Programmable Logic and Applications (FPL), 338–344.
bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for
k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE},
author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009},
pages={338–344} }'
chicago: Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator
for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE,
2009.
ieee: T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest
Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on
Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.
mla: Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning
Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), IEEE, 2009, pp. 338–44.
short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), IEEE, 2009, pp. 338–344.'
date_created: 2018-04-06T15:15:47Z
date_updated: 2023-09-26T13:52:52Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- IMORC
- NOC
- KNN
- accelerator
language:
- iso: eng
page: 338-344
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publication_identifier:
isbn:
- 978-1-4244-3892-1
issn:
- 1946-1488
publisher: IEEE
quality_controlled: '1'
status: public
title: An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2263'
abstract:
- lang: eng
text: 'In this paper, we introduce the Woolcano reconfigurable processor architecture.
The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary
Processing Unit (APU) as well as the partial reconfiguration capabilities to provide
dynamically reconfigurable custom instructions. We also present a hardware tool
flow that automatically translates software functions into custom instructions
and a software tool flow that creates binaries using these instructions. While
previous research on processors with reconfigurable functional units has been
performed predominantly with simulation, the Woolcano architecture allows for
exploring dynamic instruction set extension with commercially available hardware.
Finally, we present a case study demonstrating a custom floating-point instruction
generated with our approach, which achieves a 40x speedup over software-emulated
floating-point operations and a 21% speedup over the Xilinx hardware floating-point
unit. '
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction
Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of
Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.'
apa: 'Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow
for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.'
bibtex: '@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture
and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322}
}'
chicago: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool
Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
319–22. USA: CSREA Press, 2009.'
ieee: 'M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic
Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.'
mla: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow
for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2009, pp. 319–22.'
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.'
date_created: 2018-04-06T15:19:51Z
date_updated: 2023-09-26T13:53:30Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 319-322
place: USA
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-101-5
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension
on Xilinx Virtex-4 FX'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2358'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Stefan
full_name: Lietsch, Stefan
last_name: Lietsch
- first_name: Kris
full_name: Thielemans, Kris
last_name: Thielemans
citation:
ama: 'Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on
parallel architectures using STIR. In: IEEE Nuclear Science Symposium Conference
Record (NSS). IEEE; 2008:4161-4168. doi:10.1109/NSSMIC.2008.4774198'
apa: Beisel, T., Lietsch, S., & Thielemans, K. (2008). A method for OSEM PET
reconstruction on parallel architectures using STIR. In IEEE Nuclear Science
Symposium Conference Record (NSS) (pp. 4161–4168). IEEE. https://doi.org/10.1109/NSSMIC.2008.4774198
bibtex: '@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM
PET reconstruction on parallel architectures using STIR}, DOI={10.1109/NSSMIC.2008.4774198},
booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE},
author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008},
pages={4161–4168} }'
chicago: Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM
PET Reconstruction on Parallel Architectures Using STIR.” In IEEE Nuclear Science
Symposium Conference Record (NSS), 4161–68. IEEE, 2008. https://doi.org/10.1109/NSSMIC.2008.4774198.
ieee: T. Beisel, S. Lietsch, and K. Thielemans, “A method for OSEM PET reconstruction
on parallel architectures using STIR,” in IEEE Nuclear Science Symposium Conference
Record (NSS), 2008, pp. 4161–4168.
mla: Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures
Using STIR.” IEEE Nuclear Science Symposium Conference Record (NSS), IEEE,
2008, pp. 4161–68, doi:10.1109/NSSMIC.2008.4774198.
short: 'T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium
Conference Record (NSS), IEEE, 2008, pp. 4161–4168.'
date_created: 2018-04-17T10:59:40Z
date_updated: 2022-01-06T06:55:57Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/NSSMIC.2008.4774198
page: 4161-4168
publication: IEEE Nuclear Science Symposium Conference Record (NSS)
publisher: IEEE
status: public
title: A method for OSEM PET reconstruction on parallel architectures using STIR
type: conference
user_id: '24135'
year: '2008'
...
---
_id: '2365'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sven
full_name: Döhre, Sven
last_name: Döhre
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Ulf
full_name: Lorenz, Ulf
last_name: Lorenz
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Andre
full_name: Send, Andre
last_name: Send
- first_name: Alexander
full_name: Warkentin, Alexander
last_name: Warkentin
citation:
ama: 'Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2008:245-251.'
apa: 'Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T.,
… Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
(pp. 245–251). CSREA Press.'
bibtex: '@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008,
title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter,
Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander},
year={2008}, pages={245–251} }'
chicago: 'Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz,
Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating
GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 245–51. CSREA Press, 2008.'
ieee: 'M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2008, pp. 245–251.'
mla: 'Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2008, pp. 245–51.'
short: 'M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A.
Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.'
date_created: 2018-04-17T11:34:35Z
date_updated: 2022-01-06T06:55:58Z
department:
- _id: '27'
- _id: '78'
page: 245-251
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-064-7
publisher: CSREA Press
status: public
title: 'The GOmputer: Accelerating GO with FPGAs'
type: conference
user_id: '24135'
year: '2008'
...