---
_id: '2424'
abstract:
- lang: eng
text: ' Recent generations of high-density and high-speed FPGAs provide a sufficient
capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid
CPUs that combine standard CPU cores with reconfigurable coprocessors are an important
subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded
on demand while the CPU remains running. However, the lack of high-level design
tools for partial reconfiguration makes practical implementations a challenging
task. In this paper, we introduce a design flow to implement hybrid processors
on Xilinx Virtex. The design flow is based on two techniques, virtual sockets
and feed-through components, and can efficiently generate partial configurations
from industry-quality cores. We discuss the design flow and present a fully operational
audio streaming prototype to demonstrate its feasibility. '
author:
- first_name: Matthias
full_name: Dyer, Matthias
last_name: Dyer
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex.
In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL).
Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5'
apa: Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores
for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications
(FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5
bibtex: '@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer
Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438},
DOI={10.1007/3-540-46117-5},
booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner,
Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science
(LNCS)} }'
chicago: Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable
Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and
Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS).
Springer, 2002. https://doi.org/10.1007/3-540-46117-5.
ieee: M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx
Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL),
2002, vol. 2438, pp. 292–301.
mla: Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.”
Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol.
2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.
short: 'M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), Springer, 2002, pp. 292–301.'
date_created: 2018-04-17T15:14:39Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1007/3-540-46117-5
intvolume: ' 2438'
keyword:
- partial reconfiguration
page: 292-301
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: Springer
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partially Reconfigurable Cores for Xilinx Virtex
type: conference
user_id: '24135'
volume: 2438
year: '2002'
...
---
_id: '2425'
abstract:
- lang: eng
text: ' We present instance-specific custom computing machines for the set covering
problem. Four accelerator architectures are developed that implement branch \&
bound in 3-valued logic and many of the deduction techniques found in software
solvers. We use set covering benchmarks from two-level logic minimization and
Steiner triple systems to derive and discuss experimental results. The resulting
raw speedups are in the order of four magnitudes on average. Finally, we propose
a hybrid solver architecture that combines the raw speed of instance-specific
reconfigurable hardware with flexible bounding schemes implemented in software. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem.
In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM).
IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671'
apa: Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set
Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing
Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671
bibtex: '@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for
the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671},
booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco},
year={2002}, pages={163–172} }'
chicago: Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the
Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing
Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671.
ieee: C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering
Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines
(FCCM), 2002, pp. 163–172.
mla: Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set
Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing
Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom
Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.'
date_created: 2018-04-17T15:15:44Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/FPGA.2002.1106671
page: 163-172
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE Computer Society
status: public
title: Custom Computing Machines for the Set Covering Problem
type: conference
user_id: '24135'
year: '2002'
...
---
_id: '10651'
author:
- first_name: Michael
full_name: Eisenring, Michael
last_name: Eisenring
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The
Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946
apa: Eisenring, M., & Platzner, M. (2002). A Framework for Run-time Reconfigurable
Systems. The Journal of Supercomputing, 21(2), 145–159. https://doi.org/10.1023/a:1013627403946
bibtex: '@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable
Systems}, volume={21}, DOI={10.1023/a:1013627403946},
number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic
Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159}
}'
chicago: 'Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable
Systems.” The Journal of Supercomputing 21, no. 2 (2002): 145–59. https://doi.org/10.1023/a:1013627403946.'
ieee: M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,”
The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.
mla: Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable
Systems.” The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic
Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946.
short: M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159.
date_created: 2019-07-10T11:13:11Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1023/a:1013627403946
extern: '1'
intvolume: ' 21'
issue: '2'
language:
- iso: eng
page: 145-159
publication: The Journal of Supercomputing
publisher: Kluwer Academic Publishers
status: public
title: A Framework for Run-time Reconfigurable Systems
type: journal_article
user_id: '398'
volume: 21
year: '2002'
...
---
_id: '13611'
author:
- first_name: Herbert
full_name: Walder, Herbert
last_name: Walder
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement
and Footprint Transform. In: Proceedings of the 2nd International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press;
2002:24-30.'
apa: 'Walder, H., & Platzner, M. (2002). Non-preemptive Multitasking on FPGAs:
Task Placement and Footprint Transform. In Proceedings of the 2nd International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)
(pp. 24–30). CSREA Press.'
bibtex: '@inproceedings{Walder_Platzner_2002, title={Non-preemptive Multitasking
on FPGAs: Task Placement and Footprint Transform}, booktitle={Proceedings of the
2nd International Conference on Engineering of Reconfigurable Systems and Algorithms
(ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco},
year={2002}, pages={24–30} }'
chicago: 'Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs:
Task Placement and Footprint Transform.” In Proceedings of the 2nd International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),
24–30. CSREA Press, 2002.'
ieee: 'H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement
and Footprint Transform,” in Proceedings of the 2nd International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp.
24–30.'
mla: 'Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs:
Task Placement and Footprint Transform.” Proceedings of the 2nd International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2002, pp. 24–30.'
short: 'H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002,
pp. 24–30.'
date_created: 2019-10-04T21:13:46Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
page: 24-30
publication: Proceedings of the 2nd International Conference on Engineering of Reconfigurable
Systems and Algorithms (ERSA)
publisher: CSREA Press
status: public
title: 'Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform'
type: conference
user_id: '398'
year: '2002'
...
---
_id: '2428'
abstract:
- lang: eng
text: ' In this paper we present instance-specific accelerators for minimum-cost
covering problems. We first define the covering problem and discuss a branch&bound
algorithm to solve it. Then we describe an instance-specific hardware architecture
that implements branch&bound in 3-valued logic and uses reduction techniques usually
found in software solvers. Results for small unate covering problems reveal significant
raw speedups. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2001:85-91.'
apa: Plessl, C., & Platzner, M. (2001). Instance-Specific Accelerators for Minimum
Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA) (pp. 85–91). CSREA Press.
bibtex: '@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators
for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian
and Platzner, Marco}, year={2001}, pages={85–91} }'
chicago: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators
for Minimum Covering.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 85–91. CSREA Press, 2001.
ieee: C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,”
in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 2001, pp. 85–91.
mla: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for
Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.'
date_created: 2018-04-17T15:39:17Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
- _id: '78'
keyword:
- minimum covering
- accelerator
- funding-sundance
page: 85-91
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publisher: CSREA Press
status: public
title: Instance-Specific Accelerators for Minimum Covering
type: conference
user_id: '24135'
year: '2001'
...
---
_id: '2432'
abstract:
- lang: eng
text: In this paper, we present the analysis of applications from the domain of
handheld and wearable computing. This analysis is the first step to derive and
evaluate design parameters for dynamically reconfigurable processors. We discuss
the selection of representative benchmarks for handhelds and wearables and group
the applications into multimedia, communications, and cryptography programs. We
simulate the applications on a cycle-accurate processor simulator and gather statistical
data such as instruction mix, cache hit rates and memory requirements for an embedded
processor model. A breakdown of the executed cycles into different functions identifies
the most compute-intensive code sections - the kernels. Then, we analyze the applications
and discuss parameters that strongly influence the design of dynamically reconfigurable
processors. Finally, we outline the construction of a parameterizable simulation
model for a reconfigurable unit that is attached to a processor core.
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
- first_name: Gerhard
full_name: Tröster, Gerhard
last_name: Tröster
citation:
ama: 'Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors
for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology:
FPGAs and Reconfigurable Processors for Computing and Communications III.
Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376'
apa: 'Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001).
Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376'
bibtex: '@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc.
SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application
Analysis}, volume={4525}, DOI={10.1117/12.434376},
booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for
Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and
Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146},
collection={Proc. SPIE} }'
chicago: 'Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard
Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.”
In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376.'
ieee: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable
Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable
Technology: FPGAs and Reconfigurable Processors for Computing and Communications
III, 2001, vol. 4525, pp. 135–146.'
mla: 'Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables:
Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable
Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46,
doi:10.1117/12.434376.'
short: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable
Technology: FPGAs and Reconfigurable Processors for Computing and Communications
III, 2001, pp. 135–146.'
date_created: 2018-04-17T15:51:39Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
- _id: '78'
doi: 10.1117/12.434376
intvolume: ' 4525'
keyword:
- benchmark
page: 135-146
publication: 'Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III'
series_title: Proc. SPIE
status: public
title: 'Reconfigurable Processors for Handhelds and Wearables: Application Analysis'
type: conference
user_id: '24135'
volume: 4525
year: '2001'
...
---
_id: '10713'
author:
- first_name: Oskar
full_name: Mencer, Oskar
last_name: Mencer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Martin
full_name: Morf, Martin
last_name: Morf
- first_name: Michael
full_name: J. Flynn, Michael
last_name: J. Flynn
citation:
ama: Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers
for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration
({VLSI}) Systems. 2001;9(1):205-210. doi:10.1109/92.920835
apa: Mencer, O., Platzner, M., Morf, M., & J. Flynn, M. (2001). Object-oriented
domain specific compilers for programming FPGAs. {IEEE} Transactions on Very
Large Scale Integration ({VLSI}) Systems, 9(1), 205–210. https://doi.org/10.1109/92.920835
bibtex: '@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain
specific compilers for programming FPGAs}, volume={9}, DOI={10.1109/92.920835},
number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI})
Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn,
Michael}, year={2001}, pages={205–210} }'
chicago: 'Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. Flynn. “Object-Oriented
Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very
Large Scale Integration ({VLSI}) Systems 9, no. 1 (2001): 205–10. https://doi.org/10.1109/92.920835.'
ieee: O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain
specific compilers for programming FPGAs,” {IEEE} Transactions on Very Large
Scale Integration ({VLSI}) Systems, vol. 9, no. 1, pp. 205–210, 2001.
mla: Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming
FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems,
vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835.
short: O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very
Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210.
date_created: 2019-07-10T11:47:42Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/92.920835
extern: '1'
intvolume: ' 9'
issue: '1'
language:
- iso: eng
page: 205-210
publication: '{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems'
status: public
title: Object-oriented domain specific compilers for programming FPGAs
type: journal_article
user_id: '398'
volume: 9
year: '2001'
...
---
_id: '13463'
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK,
Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.
apa: Enzler, R., & Platzner, M. (2001). Dynamically Reconfigurable Processors.
TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).
bibtex: '@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors},
publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler,
Rolf and Platzner, Marco}, year={2001} }'
chicago: Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors.
TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
ieee: R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK,
Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
mla: Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors.
TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
short: R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK,
Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
date_created: 2019-09-30T09:27:00Z
date_updated: 2022-01-06T06:51:36Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publisher: TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)
status: public
title: Dynamically Reconfigurable Processors
type: misc
user_id: '398'
year: '2001'
...
---
_id: '6507'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Platzner M. Reconfigurable accelerators for combinatorial problems. Computer.
2000;33(4):58-60. doi:10.1109/2.839322
apa: Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems.
Computer, 33(4), 58–60. https://doi.org/10.1109/2.839322
bibtex: '@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial
problems}, volume={33}, DOI={10.1109/2.839322},
number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics
Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }'
chicago: 'Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.”
Computer 33, no. 4 (2000): 58–60. https://doi.org/10.1109/2.839322.'
ieee: M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer,
vol. 33, no. 4, pp. 58–60, 2000.
mla: Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.”
Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers
(IEEE), 2000, pp. 58–60, doi:10.1109/2.839322.
short: M. Platzner, Computer 33 (2000) 58–60.
date_created: 2019-01-08T09:45:03Z
date_updated: 2022-01-06T07:03:08Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
doi: 10.1109/2.839322
extern: '1'
intvolume: ' 33'
issue: '4'
language:
- iso: eng
page: 58-60
publication: Computer
publication_identifier:
issn:
- 0018-9162
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Reconfigurable accelerators for combinatorial problems
type: journal_article
user_id: '398'
volume: 33
year: '2000'
...
---
_id: '10606'
author:
- first_name: Michael
full_name: Eisenring, Michael
last_name: Eisenring
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable
Embedded Systems. IEE Proceedings -- Computers & Digital Techniques.
2000;147:159-165. doi:10.1049/ip-cdt:20000496
apa: Eisenring, M., & Platzner, M. (2000). Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital
Techniques, 147, 159–165. https://doi.org/10.1049/ip-cdt:20000496
bibtex: '@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems}, volume={147}, DOI={10.1049/ip-cdt:20000496},
journal={IEE Proceedings -- Computers & Digital Techniques}, publisher={IET},
author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165}
}'
chicago: 'Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital
Techniques 147 (2000): 159–65. https://doi.org/10.1049/ip-cdt:20000496.'
ieee: M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in
Reconfigurable Embedded Systems,” IEE Proceedings -- Computers & Digital
Techniques, vol. 147, pp. 159–165, 2000.
mla: Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital
Techniques, vol. 147, IET, 2000, pp. 159–65, doi:10.1049/ip-cdt:20000496.
short: M. Eisenring, M. Platzner, IEE Proceedings -- Computers & Digital Techniques
147 (2000) 159–165.
date_created: 2019-07-10T09:22:58Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1049/ip-cdt:20000496
extern: '1'
intvolume: ' 147'
language:
- iso: eng
page: 159-165
publication: IEE Proceedings -- Computers & Digital Techniques
publisher: IET
status: public
title: Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems
type: journal_article
user_id: '398'
volume: 147
year: '2000'
...